Xtensa with user defined DSP coprocessor microarchitectures

Ezer, G.

doi:10.1109/iccd.2000.878305

Cited by 9 publications

(2 citation statements)

References 5 publications

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“…The first approach, which is being adopted by such systems as Hewlett Packard's PICO project [20,1,23] and Tensilica's Xtensa [10,7], is intended to produce low-cost high-speed fixed hardware for embedded systems. The other approach attempts to take advantage of post-silicon customization through reconfigurability.…”

Section: Customized Processor Designmentioning

confidence: 99%

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Automated design of finite state machine predictors for customized processors

Sherwood

Calder

2001

Proceedings of the 28th Annual International Symposium on Computer Architecture - ISCA '01

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Customized processors use compiler analysis and design automation techniques to take a generalized architectural model and create a specific instance of it which is optimized to a given application or set of applications. These processors offer the promise of satisfying the high performance needs of the embedded community while simuhaneously shrinking design times.Finite State Machines ( FSM) are a fundamental building block in computer architecture, and are used to control and optimize all types of prediction and speculation, now even in the embedded space. The), are used for branch prediction, cache replacement policies, and confidence estimation and accuracy counters for a varieo, of optimizations.In this paper, we present a framework for automated design of small FSM predictors for customized processors. Our approach can be used to automatically generate small FSM predictors to perform well over a suite of applications, tailored to a specific application, or even a specific instruction. We evaluate the use of these customized FSM predictors for branch prediction over a set of benchmarks.

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Section: Customized Processor Designmentioning

confidence: 99%

“…Still other designs have co-processors for a given application or type of application. Xtensa [7] supports the tight integration of coprocessors into an architecture, while PICO [20,1,23] automatically generates co-processors in the form of a custom designed systolic array.…”

Section: Customized Processor Designmentioning

confidence: 99%

Automated design of finite state machine predictors for customized processors

Sherwood

Calder

2001

Proceedings of the 28th Annual International Symposium on Computer Architecture - ISCA '01

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Synthesizable HDL generation method for configurable VLIW processors

Kobayashi¹,

Kobayashi²,

Okuda³

et al.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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This paper proposes a synthesizable HDL code generation method using a processor specification description. The proposed approach can change the number of slots and pipeline stages, and dispatching rule t o assign operations to resources. In addition, designers can specify each instruction behavior using the specification language. A control logic, a decode logic, and a data path of VLIW processor are generated from the processor specification. Designers can explore ASIP design space using the proposed a p proach effectively, because the amount of description and the modification cost are small. Using this approach, it took about eight hours to design 36 VLIW processors. Moreover, this approach provides a 82% reduction on the average compared t o the description of the HDL code.able HDL Generation for Pipelined Processors from a Micrrr Operation Description," IEICE Tmnsoctions on Fundamen-

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