Verification of Digitally Calibrated Analog Systems with Verilog-AMS Behavioral Models

Peruzzi, Robert

doi:10.1109/bmas.2006.283462

Cited by 6 publications

(2 citation statements)

References 1 publication

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“…On the other hand run-time verification methods such as [4,18,16] require simulation of the integrated AMS design. Typically the integrated designs that we refer to are so large that adequate functional verification through mixed-signal simulation of the integrated netlist is infeasible in practice, as also observed by the author of [21]. At the same time the full functionality of the component blocks is typically not required for verifying the correctness of the integration.…”

Section: Introductionmentioning

confidence: 94%

A static verification approach for architectural integration of mixed-signal integrated circuits

et al. 2010

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Section: Introductionmentioning

confidence: 94%

A static verification approach for architectural integration of mixed-signal integrated circuits

et al. 2010

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“…The models are later replaced by components which are described at transistor level or netlist level as the component designs are finalized. Using models on different abstraction levels allows the newly designed components to be verified as part of the whole system already in the early stages of the chip design [9][10][11][12].…”

Section: Mixed-signal Simulationmentioning

confidence: 99%

High level verification of the VFAT3 ASIC for CMS GEM detectors

Petrow¹,

Aspell²,

Ciaglia³

et al. 2021

J. Inst.

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A front-end readout chip VFAT3 was designed for the muon detector gas electron multipliers (GEM). GEMs were installed at the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN for the high luminosity upgrade. The design of the VFAT3 uses 790 analog and 172 digital blocks which are highly integrated, thus it is crucial to ensure that the different blocks work together and the chip works as a whole. Mixed signal simulation methods were used to verify the high level functionality. Trigger latencies of 125, 150, 175 and 225 ns were found for front-end peaking times of 25, 50, 75 and 100 ns, respectively. The maximum trigger rate for reading out standard data packets was found to be 1.7 MHz. Results of the VFAT3 high level verification are presented and the simulation methods described.

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High performance 14-bit pipelined redundant signed digit ADC

Narula

Pandey

2016

J. Semicond.

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A novel architecture of a pipelined redundant-signed-digit analog to digital converter (RSD-ADC) is presented featuring a high signal to noise ratio (SNR), spurious free dynamic range (SFDR) and signal to noise plus distortion (SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC (residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

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Verification of Digitally Calibrated Analog Systems with Verilog-AMS Behavioral Models

Cited by 6 publications

References 1 publication

A static verification approach for architectural integration of mixed-signal integrated circuits

A static verification approach for architectural integration of mixed-signal integrated circuits

High level verification of the VFAT3 ASIC for CMS GEM detectors

High performance 14-bit pipelined redundant signed digit ADC

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