Verification of Split&amp;Shift techniques for CNN hardware reduction

Fernandez-Garcia, N.A.; Albó-Canals, Jordi; Brea, V.M.; Riera-Babures, J.; Cabello, D.; Vilasís-Cardona, X.

doi:10.1109/ecctd.2007.4529543

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…We have also analyzed the hardware consequences of the S&S application over a 30 × 30 FPGA implementation realized with this purpose in . There we had a saving of 14 logic elements (LEs) per cell over 27 when reducing the number of multipliers from nine to three CC.…”

Section: Validationmentioning

confidence: 99%

Split and shift methodology on cellular processor arrays: area saving versus time penalty

Fernandez

Brea

Cabello

2012

Circuit Theory & Apps

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This paper addresses the so-called split and shift methodology. This methodology deals with the implementation of kernels of sizes that go above the physically implemented resources (local connections and weighting circuits) on synchronous cellular processor arrays (CPA), including the realization of large neighborhood operations and/or the reduction of the available hardware in order to drop the area consumption. Two main goals are pursued in the development of the methodology, namely: (1) minimum penalty at processing time and (2) absolutely no penalty at functional level. The paper presents different techniques and guidelines for the methodology application and introduces a Figure of Merit to evaluate them by relating area gains with time penalty. This, along with a kernel shape analysis, led us to propose more adequate configurations of weighting circuits and to justify the classical choice of North-East-West-South connectivity. To validate the methodology, we realize several estimates over actual physical implementations, and we propose the realization over CPAs of the spin filters, scale invariant feature transform and speeded-up robust features algorithms. A more in-depth trade-off analysis is realized over the implementation of the pixel level snakes algorithm.but it can interact with separated PEs, thanks to the propagative effects of the array dynamics of kernel application. The basic characteristic of local connectivity and its simple SIMD control makes this kind of systems very suitable for hardware implementation. However, as a consequence, the natural size of the kernels to be applied is limited to the smallest one (3 Â 3). This is, on the other hand, an important limitation in the functionality of a CPA as larger neighborhoods are needed in several image processing primitives as diffusion or low-pass filtering operations [1], halftoning [2], texture analysis [3] or matching and hit&miss operations [4], some of them used in algorithms like modern scale-and rotation-invariant feature extractors like scale invariant feature transform (SIFT) and speeded-up robust features (SURF) [5,6].As indicated, a CPA can realize global processing taking into account the whole image information thanks to the propagative effects of the architecture. According to this we can think in solving the remote neighbors interaction through the recursive application of templates. In fact, a recursive process can be summarized in the application of a large neighborhood (LN) template. Nevertheless, the inverse process, the decomposition of a LN template into minimum-sized templates is not trivial, and different approaches have been developed to deal with this issue.The challenge is then to implement any kind of LN operations while keeping the local connectivity and with affordable penalties in performance. Our goal is to do it, in addition, with the minimum impact in the architecture at hardware level.On the other hand, on focal-plane processors with a pixel-to-PE assignment, the area occupation is not only a matter of cost or h...

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Section: Validationmentioning

confidence: 99%

Split and shift methodology on cellular processor arrays: area saving versus time penalty

Fernandez

Brea

Cabello

2012

Circuit Theory & Apps

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“…The emulation of a full parallel CNN at individual neuron level requires a huge amount of area on FPGA, then this approach would be realistically applicable only to small networks, unless some special arrangements are made [13]. Therefore, we resorted to implement the intrinsic convolutional structure of the DT-CNN on the parallel hardware of the FPGA.…”

Section: Cnn Modelmentioning

confidence: 99%

Optimized cellular neural network universal machine emulation on FPGA

Pazienza

Bellana-Camanes

Riera-Babures

et al. 2007

2007 18th European Conference on Circuit Theory and Design

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An FPGA architecture to emulate a single-layer Cellular Neural Network -Universal Machine (CNN-UM) is proposed. It is based on a fast realization of the CNN convolution operation on the parallel hardware of the FPGA. The setup is capable of performing a CNN iteration over a 30×30 pixel image in less than 30 µs. Moreover, this platform has been used to realize the visual system of an autonomous mobile robot.

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