Verilog HDL methodology for redundancy in digital circuits targeting FPGA technology for highly reliable applications

Abstract

Fault tolerance represents the foundation for critical systems, providing reliable computation and control in a broad range of applications. This is a major area of interest for aerospace and military applications. The need for fault tolerant systems in terrestrial applications is of growing importance also. In such systems, fault tolerance is achieved through redundancy, increasing implementation complexity and costs. This paper presents a methodology for implementing redundant digital circuits using Verilog HDL and targeting FPGA technology. Various redundant digital circuits are presented. For the simulation and implementation of the circuits, Cadence NC and Xilinx design tools were used.

A framework to quantify FPGA design hardness against radiation-induced single event effects

“…Unfortunately, there is currently no capability to quantify the benefit from a specific design mitigation method after inserting it into a design without extensive quantitative testing. Additionally, verification of proper mitigation implementation is important, especially as synthesis tools have been observed to remove intentionally placed error correction circuitry after "optimizing" the circuit and classifying the mitigation as redundant [3]. For these reasons, it is very difficult for FPGA designers to ensure a reliable design without performing a significant amount of additional work.…”