Vertical Assembly of Carbon Nanotubes for VLSI Via Interconnection

Abstract

As VLSI technologies scale down, the performance of copper interconnects is greatly degraded by the electromigration problems. The alternative interconnect materials need to be developed. Carbon nanotubes (CNTs) have emerged as a promising nanostructured materials for interconnect applications in the future integrated circuits (ICs) due to their unique molecular structure and excellent properties. In this paper, we have developed a new via interconnection technique by employing alternating current dielectrophoresis (AC-DEP) of the CNT bundles at room temperature. By predefining via holes, high density CNTs have been successfully assembled using AC-DEP technique between the top and bottom electrodes. Our method is controllable, scalable and also compatible with conventional CMOS process, which demonstrates that the carbon nanotubes can be used as interconnects in future VLSI circuits.