Vertical MOS transistors with 70 nm channel length

Risch, L.; Krautschneider, Wolfgang H.; Hofmann, Franz; Schäfer, H.; Aeugle, T.; Rosner, W.

doi:10.1109/16.535340

Cited by 58 publications

(14 citation statements)

References 4 publications

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“…These devices also offer a steeper sub-threshold slope because the surround gate provides better control of the channel. Thick pillar, surround gate, v-MOSFETs have also been researched because they offer lithography-independent channel length scaling, decoupling of the gate length from the packing density and an improved current drive per unit silicon area compared with conventional lateral CMOS [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Hakim

Tan

Buiu

et al. 2009

Solid-State Electronics

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a b s t r a c tThis paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of subthreshold slope as the channel length is reduced from 250 to 100 nm, with 100 nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is investigated using a frame-gate architecture in which the polysilicon gate overlaps the side of the pillar, thereby protecting the channel from etch damage. This device shows no degradation of short channel effects when the channel length is scaled and exhibits a near-ideal sub-threshold slope of 76 mV/dec and a DIBL of 33 mV/V at a channel length of 100 nm. Gated diode measurements unambiguously demonstrate that this improved sub-threshold slope is due to the elimination of etch damage at the top and bottom of the pillar created during polysilicon gate etch. An alternative method of eliminating dry etch damage is then investigated by optimizing the Fillet Local Oxidation (FILOX). These devices give a sub-threshold slope of 81 mV/dec and a DIBL of 25 mV/V at a channel length of 100 nm. The improved immunity to dry etch damage is due to the creation of a thick protective oxide at the top and bottom of the pillar during the FILOX process.

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Section: Introductionmentioning

confidence: 99%

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

Hakim

Tan

Buiu

et al. 2009

Solid-State Electronics

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“…In addition, compared to planar concepts using the same lithographic resolution, the packing density is improved by a certain factor, which depends on the application (e.g. the factor is 2.4 for [3]). …”

Section: Introductionmentioning

confidence: 98%

“…To avoid the limitation of lithography, MOSFET concepts based on a vertical layout have been developed [3,4]. The channel length is not defined by lithography but by the thickness of an epitaxial layer and can easily be scaled down into the sub-100 nm region.…”

Section: Introductionmentioning

confidence: 99%

Vertical silicon MOSFETs based on selective epitaxial growth

Moers¹,

Tonnesmann

Klaes

et al.

ASDAM 2000. Conference Proceedings. Third International EuroConference on Advanced Semiconductor Devices and Microsystems (Cat.

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Two vertical MOSFET concepts using selective epitaxial growth (SEC) by low pressure chemical vapour deposition (LPCVD) are proposed and measured device characteristics are presented. I n the VFET concept, the gate oxide is grown afer epitaxy, while in the VOXFET concept, the gate oxide is prepared before the channel region is grown. P-channel MOSFETs with channel lengths down to lOOnm have been fabricated. The VFET with LG = 200nm obtains a transconductance g , of 135mS/mm and a sub-threshold slope of S = 105 mV/dec. Measured &cut offfrequencies of the VFETare fT = 1.9 G H z andJ,l,x = 1.2 GHz. The dc-characteristics of the VOXFET are comparable, (LG = 100nm; dtjx = 10nm; g,,, = 200mS/mm), but its layout reduces parasitic capacitances, so it show better $-performance I~T = 8.7 GHz andf,,, = 19.2 GHz).

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“…Vertical MOSFETs are potential candidates in the longer term to replace mainstream lateral devices because they offer a number of important advantages [1][2][3]. First, the channel length is defined using techniques other than lithography, for example epitaxy or ion implantation.…”

Section: Introductionmentioning

confidence: 99%

“…Second, self-aligned double and surround gates can readily be realised with easy access to the gates. Third with surround gates, vertical MOSFETs offer increased current drive per unit silicon area [1][2][3]. However, vertical MOSFETs have one important disadvantage, which is higher overlap capacitances than conventional lateral devices, which has made them less competitive compared with their lateral counterpart.…”

Section: Introductionmentioning

confidence: 99%