Abstract-Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50 nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented. A new process that uses spacer or fillet local oxidation is developed to reduce the overlap capacitance between the gate and the source/drain electrodes. Electrical characteristics of surround gate n-MOSFETs are presented and compared with characteristics from single gate and double gate devices on the same wafer. Transistors with channel length down to 100 nm have been realised. They show good symmetry between the source on top and source on bottom configuration and subthreshold slope down to 100 mV. The short channel effects of the surround gate MOSFETs are investigated.

exhibits the same trend with their gate diode characteristics, where the higher Al content devices present the lower gate leakage current, and all leakage currents are increased by increasing the input rf powers. IV. CONCLUSIONIn summary, the AlxGa10xAs=InGaAs (x = 0.3, 0.5, 0.7, 1) DCFETs on GaAs substrates were fabricated and characterized. Based on the experimental evaluations, we conclude that for the aluminum content of Al0:5Ga0:5As, i.e. x = 0:5, is the best composition to realize DCFETs in terms of device dc and RF characteristics. Although higher Al content devices ( x = 0.7, 1) can further enhance the Schottky diode performance; however, due to the inferior material quality and higher parasitic resistance, the device characteristics degrade. The dc peak extrinsic g m of Al 0:5 Ga 0:5 As/In 0:15 Ga 0:85 As DCFETs is 272 mS/mm, together with an f T of 13 GHz and an f max of 25 GHz. As to the power performance at 2.4 GHz, it demonstrates a 15-dBm saturated output power, a 16.5-dB linear power gain and a 20% efficiency. As barrier on the low-temperature density and mobility of the two-dimensional electron gas in GaAs/AlGaAs modulation-doped heterostructure," Appl. Phys. Lett, vol. 66, no. 11, pp. 1406Lett, vol. 66, no. 11, pp. -1409Lett, vol. 66, no. 11, pp. , 1995 [5] Y. Bito, T. Kato, and N. Iwata, "Enhancement-mode power heterostructure FET utilizing Al Ga As barrier layer with negligible operation gate current for digital cellular phones," IEEE Trans. Electron Devices, vol. 48, pp. 1503-1509 M. T. Yang and Y. J. Chan, "Device linearity comparisons between doped-channel and modulation-doped designs in pseudomorphic Al Ga As/In Ga As heterostructures," IEEE Trans. Electron Devices, vol. 43, pp. 1174-1180, Aug. 1996. Design of 50-nm Vertical MOSFET Incorporating a Dielectric PocketD. Donaghy, S. Hall, C. H. de Groot, V. D. Kunz, and P. AshburnAbstract-A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of shortchannel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.

Abstract-Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from −50 to 200• C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical 110 pillar sidewalls and the horizontal 100 wafer surface.Index Terms-Band-to-band tunneling, body leakage, fillet local oxidation (FILOX), gate-induced drain leakage (GIDL), leakage current, vertical MOSFET.

Abstract-This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.