Reduction of parasitic capacitance in vertical mosfets by spacer local oxidation

Abstract

Abstract-Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation

“…These devices also offer a steeper sub-threshold slope because the surround gate provides better control of the channel. Thick pillar, surround gate, v-MOSFETs have also been researched because they offer lithography-independent channel length scaling, decoupling of the gate length from the packing density and an improved current drive per unit silicon area compared with conventional lateral CMOS [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21].…”

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

“…A sacrificial oxidation was performed to eliminate dry etch damage and reduce the surface roughness on the pillar sidewall. After stripping of this oxide, a 10-nm stress relief oxide was thermally grown at 900 • C. For the FILOX process [15], a 90-nm silicon nitride was deposited at 720…”

“…However, v-MOSFETs have several important disadvantages, i.e., high overlap capacitance, dry etch damage on the pillar sidewall, and lack of an appropriate silicidation technology. The problem of overlap capacitance has been addressed using Fillet Local OXidation (FILOX) [15], [16]. In this process, a thicker oxide is grown at the bottom and top of the active pillar using nitride spacer to suppress oxidation on the pillar sidewall.…”

“…Dry etch damage occurs during pillar dry etch and polysilicon gate etch, and degrades the subthreshold slope. Damage occurring during pillar dry etch can be eliminated by sacrificial oxidation, and we have recently shown how the device architecture and the FILOX process [15] can be optimized to eliminate dry etch damage during silicon gate etch and deliver excellent values of subthreshold slope [18], [19]. However, to date, there have been no reports in the literature on silicidation technologies for surround-gate v-MOSFETs.…”

Recent developments in deca-nanometer vertical MOSFETs

“…Notice that the transistor can be considered to operate in either source up, or down modes although not all architectural features are appropriate for bi-directional operation. Specifically we identify the use of a so-called dielectric pocket (DP) to control SCE (source down mode) [2,3], thickened oxide regions, including a novel fillet oxidation (FILOX) overlap process to minimize overlap capacitance [2,4] and the use of polySiGe regions to reduce the emitter efficiency of the PBT (source up mode) [5]. We now consider these concepts, and indicate the expected performance advantage in the ITRS context.…”