Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Abstract

Abstract-Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from −50 to 200• C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical 110 pillar sidewalls and the horizontal 100 wafer surface.Index Terms-Band-to-band tunneling, body leakage, fillet local oxidation (FILOX), gate-induced drain leakage (GIDL), leakage current, vertical MOSFET.

Evaluation of Device Fabrication from FET to CFET: A Review

“…In DG MOSFETs, two different modes of operation are possible depending on their work function due to the two-gate structure. [20] 06030-4 Symmetric DG (SDG) MOSFET. When both gates have identical material or work function, then the structure is known as symmetric DG MOSFET.…”

“…Both gates are connected exactly with same bias. In the on-state, two conducting channels (inversion layers) are framed on two sides of the silicon body in the SDG device [20]. In the meantime, both channels are on.…”

“…These have two different work functions of both gates. DG MOSFET switching can be obtained by applying different voltages to both gates [20]. Just a single channel is made for the ADG device unless the operation voltage is high to form another reverse layer near the P + gate.…”

Investigation of short channel immunity of fully depleted double gate MOS with vertical structure

“…From several available double gate concepts, vertical MOSFET has gained some grounds. Applying vertical structure of MOSFET in the nanometer scale offers several benefits, which have been promoted by a number of researchers [6][7][8]. The ability to handle the lithography-bounded problem, by its relaxed-lithography process for adjusting the channel length into vertical layer definition is well-known.…”

Simulation of Two-Dimensional 50 nm Vertical Metal Oxide Semiconductor Field-Effect Transistor Incorporating a Dielectric Pocket

“…[2][3][4] Firstly, gate length is defined by nonlithographic methods. This enables the realization of a smaller channel length without using advanced lithography methods.…”