Very High-Performance 24-Channels Time-to-Digital Converter in Xilinx 20-nm Kintex UltraScale FPGA

Lusardi, N.; Garzetti, F.; Corna, N.; Marco, R. De; Geraci, A.

doi:10.1109/nss/mic42101.2019.9059958

Cited by 20 publications

(9 citation statements)

References 4 publications

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“…For this reason, the potential directions for the next developments in the BrightEyes-TTM project would be the migration to a new FPGA-development kit equipped with ARM-based processors. In this case, it might be interesting exploring next generation FPGAs with improved technological node (e.g., Ultrascale 20nm), on which TDCs with superior performances are demonstrated 36 .…”

Section: Discussionmentioning

confidence: 99%

The BrightEyes-TTM as an open-source time-tagging module for democratising single-photon microscopy

et al. 2022

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Fluorescence laser-scanning microscopy (LSM) is experiencing a revolution thanks to new single-photon (SP) array detectors, which give access to an entirely new set of single-photon information. Together with the blooming of new SP LSM techniques and the development of tailored SP array detectors, there is a growing need for (i) DAQ systems capable of handling the high-throughput and high-resolution photon information generated by these detectors, and (ii) incorporating these DAQ protocols in existing fluorescence LSMs. We developed an open-source, low-cost, multi-channel time-tagging module (TTM) based on a field-programmable gate array that can tag in parallel multiple single-photon events, with 30 ps precision, and multiple synchronisation events, with 4 ns precision. We use the TTM to demonstrate live-cell super-resolved fluorescence lifetime image scanning microscopy and fluorescence lifetime fluctuation spectroscopy. We expect that our BrightEyes-TTM will support the microscopy community in spreading SP-LSM in many life science laboratories.

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Section: Discussionmentioning

confidence: 99%

The BrightEyes-TTM as an open-source time-tagging module for democratising single-photon microscopy

et al. 2022

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“…All DI configurations are 00000000 and SI configurations are 11111111. Once the coordinates of CARRY8 are constrained, all CARRY8 become a chain state arrangement, also known as TDL [ 24 ]. D Flip-Flop (DFF) samples C0–C7 (outputs of eight MUXs) and O0–O7 (outputs of eight XORs).…”

Section: System Architecturementioning

confidence: 99%

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Zhang

Zhao

Chen

et al. 2022

Sensors

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A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB.

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“…5-core 2D-Vernier TDCs [22] achieved similar performances but used 28-fold more LUTs than our WU TDC. Multichain 0.3 ps resolution TDCs [52] had limited precision (< 8.50 ps), but their linearity was not revealed at all. 20-chain TDCs [53] used 8-fold (another multi-chain TDC [54] produced worse precision and used 3-fold more LUTs) LUTs, 2-fold flipflops (FFs) and 6-fold BRAMs more than our DSWU TDC.…”

Section: Discussion and Comparisonsmentioning

confidence: 98%

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

Xie

Chen

2022

IEEE Trans. Ind. Electron.

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The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, an earlier study concluded that the WU method is not suitable for UltraScale fieldprogrammable gate array (FPGA) devices, due to more severe bubble errors. This paper proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new subtapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDCs combining the dual sampling (DS) structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square (RMS) resolution. Compared with previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs.Index Terms-Carry chains, field-programmable gate array (FPGA), time-of-flight (ToF), time-to-digital converter (TDC) Manuscript

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Very High-Performance 24-Channels Time-to-Digital Converter in Xilinx 20-nm Kintex UltraScale FPGA

Cited by 20 publications

References 4 publications

The BrightEyes-TTM as an open-source time-tagging module for democratising single-photon microscopy

The BrightEyes-TTM as an open-source time-tagging module for democratising single-photon microscopy

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

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