Very‐large‐scale integration implementation of a convolutional neural network accelerator for abnormal heartbeat detection

Abstract

In this study, a very-large-scale integration implementation of a convolutional neural network (CNN) inference for abnormal heartbeat detection was proposed. Four-lead electrocardiogram signals were used to detect abnormal heartbeat conditions, such as premature ventricular complex. 1D CNNs and fully connected layers were utilised in the proposed chip to achieve high-speed, small-area, and high-accuracy arrhythmia detection. The proposed chip was implemented using a 90-nm complementary metal-oxide-semiconductor process and operated at 125 MHz with a 0.67 mm 2 core area. The power consumption was 4.18 mW at high-speed operation frequency (125 MHz) and 3.79 mW at 10 kHz for low-power applications. The detection accuracy was 95.14% based on the MIT-BIH arrhythmia database. Consequently, the properties of high speed, low power, small area, and high accuracy were established in the proposed accelerator chip.

Spike‐driven gated recurrent neural network processor for electrocardiogram arrhythmias detection realised in 55‐nm CMOS technology

“…A summary of this work specification and other previous designs are illustrated in Table 2. This work achieves better classification accuracy, adapting gated recurrent neural network than other works [2–5 ], and lower power consumption is achieved by using asynchronous spike‐driven logic.…”

“…To achieve a target to automate arrhythmia monitoring, several ECG-based detections have been reported by using artificial intelligence processors [2][3][4][5]. In [2], a very-large-scale integration implementation was proposed using a convolutional neural network (CNN) layer and a fully connected neural network (FNN) layer inference models for abnormal heartbeat detection. This chip utilised a one-dimensional (1D) CNN layer and a fully connected layer to process the ECG signal as a 2D image, achieving 95.14% in detecting arrhythmia.…”

A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN)

“…In general, our proposed work offers several advantages over the previous works. First, the proposed work achieves high classification accuracy while occupying a relatively smaller area, making it more compact compared to the previous works as proposed by [16] and [17]. In addition, the proposed DSNN circuit consumes only 0.75mW of power, which is significantly lower than both circuits as proposed by [16] and [17].…”

“…As a result, once a deep learning model is trained, it can be used to classify ECG signals into a number of arrhythmic events. In such aspects of applications, VLSI implementations of CNNbased techniques for abnormal heartbeat detection were proposed in previous studies in literature [16]- [17]. The results obtained from these works have shown that the hardware realization of CNN for ECG heartbeat classification may achieve high speed, small area, and low power dissipation with a high detection rate, thus improving early detection and timely treatment of cardiac disorders.…”

“…First, the proposed work achieves high classification accuracy while occupying a relatively smaller area, making it more compact compared to the previous works as proposed by [16] and [17]. In addition, the proposed DSNN circuit consumes only 0.75mW of power, which is significantly lower than both circuits as proposed by [16] and [17]. Also, although the proposed work operates at a lower frequency of 20M Hz compared to [16] and [17], it still offers a reasonable operating frequency for ECG abnormal heartbeat classification.…”