Very low energy implanted Bragg gratings in SOI for wafer scale testing applications

Abstract

-We present Bragg gratings with an effective index change introduced by implanting germanium at only 15KeV. An extinction ratio of 35dB at 1350nm is demonstrated for device lengths of 600μm, furthermore laser annealing is demonstrated. IntroductionIn the information age current technologies struggle to deliver the data rates required by modern communications and computer bus systems. Silicon photonics has the potential of overcoming some of these obstacles by relying on a well understood material system and technology [1]. However the full adoption of silicon based photonics would require complex integrated optoelectronic systems to be manufactured in high volumes at low costs. These requirements cannot be met without enabling a wafer scale testing [2] strategy in a similar fashion to what has been happening for many decades in the integrated electronics industry. The current challenge for silicon photonics in this area is represented by the inability of the light signal to access a processed wafer without substantially modifying the wafer surface. Most of the solutions presented for light coupling into test samples rely on substantially modifying the structure of the material to enable end fire coupling, prism coupling [3], inverted tapers [4], and cantilever structures [5]. Introducing these kinds of test points, or even wavelength selective test points such as etched or metal gratings on a processed wafer can potentially introduce undesired alterations of the light propagation, such as scattering and losses, as well as interfering with successive processing steps. In order for optical wafer scale testing to become a viable technology, optical wafer scale testing should be implemented as a minimally intrusive technology. The use of ion implanted optical structures is particularly suited for these applications, as the refractive index change can be introduced on the wafer surface without altering the general topography of the wafer. Furthermore, since the planarity of the wafer is retained, it could be possible to employ these structures for applications that require extensive surface interaction such as bonding or flip chip interactions, and sensing. The use of a low energy/low dose implant conditions (10 15 ion/cm 2 , as opposed to general doping densities which can reach 10 19 ion/cm 2 ) potentially allows minimal optical losses to be introduced by the implantation process.

Planar surface implanted diffractive grating couplers in SOI

“…The King software package can quickly and efficiently simulate the depth and level of lattice disorder, whilst King 3D can expand on this information with a more lengthy simulation to show the 3D disorder profile with greater accuracy. Using this software, a simulated level of 80% lattice disorder represents amorphisation with the desired change in refractive index of approximately 0.5, this has been shown to be in good agreement with the damage profiles observed by TEM imagery [28][29][30].…”

“…Interface regions can be substantially reduced by implanting at room temperature. When the implant is performed at room temperature these regions are not present due to dynamic annealing effects which occur during implantation [32], as verified via TEM images of similar implant designs [28,29]. Utilising room temperature implantation also reduces the time and cost of the implantation process.…”

Erasable diffractive grating couplers in silicon on insulator for wafer scale testing

“…Simulation software packages, King (2D) and King 3D [16], have been shown to be in good agreement with the damage profiles observed by TEM imagery of similar implant designs to those considered here [4,10]. Both King packages share the same core method for calculating lattice damage, which is the Monte-Carlo binary collision approximation simulation method.…”

“…A CMOS compatible concept for wafer scale testing was not presented until 2011. The method used erasable Bragg grating reflectors [3,4] to reflect light travelling in the waveguide, such that the light can then be collected by using a circulator and detector arrangement connected to the circuit input. This offers an excellent wafer scale testing methodology for devices spanning a small wavelength range, with typical devices offering a few nanometres wavelength reflectivity, but broadband operation is problematic.…”

Temporary Grating Coupler Structures Using Localised Refractive Index Engineering

“…A CMOS compatible concept for wafer scale testing was presented later in 2011. The method used erasable Bragg grating reflectors [4,5] to reflect light travelling in the waveguide, such that the light can then be collected by using a circulator and detector arrangement connected to the circuit input. This offers a wafer scale testing capability for devices spanning a small wavelength range, with typical Bragg gratings offering a few nanometres wavelength reflectivity.…”