VHDL‐AMS in switched‐current analog filter pair design based on a gyrator‐capacitor prototype circuit

Handkiewicz, Andrzej; Katarzyński, Piotr; Szczęsny, Szymon; Naumowicz, Mariusz; Melosik, Michał; Śniatała, Pawel

doi:10.1002/jnm.1921

Cited by 8 publications

(6 citation statements)

References 13 publications

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“…. v x nodes and is connected to the suitable node with block of switches SWITCHES 13 or SWITCHES 14 , respectively. The blocks are controlled using W sp and W sm words.…”

Section: Routing Of Arraymentioning

confidence: 99%

“…The inductor L was replaced by a gyrator-capacitor circuit (I G1 − C4 − I G2) [13,21]. Parameters of the gyrator-capacitor prototype were calculated using the method proposed in [15].…”

Section: Elliptic Filtermentioning

confidence: 99%

“…Colour space conversion is often carried out in order to eliminate the chrominance component of the image, followed by a compression, using a 2-dimensional discrete Fourier transform (2D-DCT 13 ). This section presents results of The idea of the 2D-DCT has been repeatedly discussed in the literature [2].…”

Section: Image Processorsmentioning

confidence: 99%

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Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR = 40.42 dB, 2D-DCT processor with PSNR = 53.05 dB and RGB-to-YCrCb converter with PSNR = 46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

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“…. v x nodes and is connected to the suitable node with block of switches SWITCHES 13 or SWITCHES 14 , respectively. The blocks are controlled using W sp and W sm words.…”

Section: Routing Of Arraymentioning

confidence: 99%

“…The inductor L was replaced by a gyrator-capacitor circuit (I G1 − C4 − I G2) [13,21]. Parameters of the gyrator-capacitor prototype were calculated using the method proposed in [15].…”

Section: Elliptic Filtermentioning

confidence: 99%

See 1 more Smart Citation

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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“…W szczególności uwidacznia się to w projektowaniu precyzyjnych filtrów mających swoje zastosowania w wielu różnych aplikacjach związanych z przetwarzaniem sygnału [1,2,3]. Niniejsza praca, na przykładzie układów z przełączanymi prądami, pokazuje nowatorskie podejście do rozwiązania takich problemów, a opisana metoda będzie zilustrowana przykładem pary filtrów pracującej w trybie przełączanych prądów [4]. Należy przede wszystkim zaznaczyć, że właściwości obwodów pracujących w trybie prądowym są mało wrażliwe na obniżanie napięcia zasilającego.…”

Section: Wprowadzenieunclassified

Optymalizacja banków filtrów z przełączanymi prądami dla technologii CMOS w nano-skali

Naumowicz

Handkiewicz

Szczęsny

2016

ELECTROTECHNICAL REVIEW

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Optymalizacja banków filtrów z przełączanymi prądami dla technologii CMOS w nano-skali Streszczenie. W artykule omówiono problem projektowania i optymalizowania układów analogowych pracujących w trybie przełączanych prądów. Technologia CMOS z tranzystorami o rozmiarach kanałów mniejszych niż kilka dziesiątek nm. jest wzięta pod uwagę. Zaprezentowano metodę optymalizacji charakterystyki częstotliwościowej z uwzględnieniem eliminacji zjawiska offsetu w odpowiedzi czasowej analogowych układów scalonych. Procedura projektowania bazuje na algorytmie Hooke'a-Jeeves'a zmodyfikowanym pod kątem optymalizacji dyskretnej. Wyniki przedstawiono dla pary filtrów piątego rzędu pracującej w trybie przełączanych prądów. Otrzymane rezultaty niemal całkowicie pokrywają się z charakterystykami idealnymi, świadcząc o skuteczności zaproponowanej metody optymalizacji.

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“…In [29] is shown that among analog integrating filters the best properties has the second order filter having two equal real poles. Also are given recommendations how to provide the required accuracy and sufficient decay rate for transients in the filter itself.…”

mentioning

confidence: 99%

Selection of Digital Filter for Microprocessor Protection Relays

Solovev¹

2018

IJECE

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The article considers some issues related to replacement of electromechanical relays used for protection of power facilities with microprocessor relays. One of the urgent problems connected with implementation of microprocessor overcurrent protections is how to use current transducers other than usual current transformers and in particular Rogowski coils that become more and more widespread. In the article are compared twelve methods of synthesis of a digital filter basing on the analog prototype -second-order integrating filter. The bilinear filter and Boxer-Thaler filters are analyzed in respect to their use in microprocessor relays. Basing on the research results a technique for selection of parameters of digital integrating filters for microprocessor relays is proposed. Simulation results show that Boxer-Thaler and bilinear filters have better accuracy during transient current measurements than the analog filter. The study allows concluding that in many cases the digital second-order bilinear filter is the best choice for use in microprocessor relays.

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VHDL‐AMS in switched‐current analog filter pair design based on a gyrator‐capacitor prototype circuit

Cited by 8 publications

References 13 publications

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

Optymalizacja banków filtrów z przełączanymi prądami dla technologii CMOS w nano-skali

Selection of Digital Filter for Microprocessor Protection Relays

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