VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems

Low Complexity FFT/IFFT Processor Applied for OFDM Transmission System in Wireless Broadband Communication

“…Multiplication with W 16 4 simply can be done by swapping from real to imaginary part and vice versa, followed by changing the sign [7]. The rest of complex multiplications are non-trivial multiplications.…”

“…The MDC (Multipath Delay Commutator) pipeline architecture is considerably adequate to attain these ends [15], and ideal choice to implement high speed long-size FFT due to its regular structure and simple control [8]. R2MDC (Radix-2 Multipath delay Commutator) structure was adopted as pipeline approach in our design for the purpose of minimizing the memory resources and saving silicon area in FPGA [16]. Moreover, the efficiency of the pipeline FFT processor can be improved by optimizing the structure and saving hardware resources [17].…”

“…Consequently, the 16-bits fixed point is more suitable to implement the proposed FFT architecture. 16 4 is simply done by swapping from real to imaginary part and vice versa, followed by changing the sign [18]. The implementation complexity of non-trivial twiddle factors W 16 2 and W 16 6 is reduced even further, due to replacement of the complex multiplications by basic operations.…”

“…16 4 is simply done by swapping from real to imaginary part and vice versa, followed by changing the sign [18]. The implementation complexity of non-trivial twiddle factors W 16 2 and W 16 6 is reduced even further, due to replacement of the complex multiplications by basic operations. However, the multiplication with W 16 2 and W 16 6 was done by add and shift operations [18], [19] (Fig.…”

A Novel RTL Architecture for FPGA Implementation of 32- Point FFT for High-Speed Application

“…In this paper, an optimized implementation of the 8-point FFT processor with the radix-2 algorithm in R2MDC architecture was proposed. The BU unit will minimize the multiplicative complexity of the FFT processor with the help of shift and add operations and it uses the less amount of the resource usage [8]. R2MDC architecture based FFT implementation will be minimizing the number of complex multiplications [9].…”