Virtual circuit switch based orderly delivery of packets in adaptive NoC routing

Das, Tuhin Subhra; Ghosal, Prasun; Chatterjee, Navonil

doi:10.1145/3356045.3360719

Cited by 4 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Ref. [ 18 ] proposes a solution that guarantees in-order packet delivery while packets are routed through multiple paths in the network, and [ 19 ] proposes a solution that supports in-order packet delivery under adaptive routing by reserving an alternate virtual path during the VC allocation process. Yet, such approaches are relatively expensive to implement in terms of silicon footprint and have high power consumption due to the extensive use of buffers.…”

Section: Related Workmentioning

confidence: 99%

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

View full text Add to dashboard Cite

Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

show abstract

Section: Related Workmentioning

confidence: 99%

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

View full text Add to dashboard Cite

show abstract

“…Wormhole switching with VCs ensures in-order packets delivery if all packets of a same flow take the same route. [5] proposes a solution that guarantees in-order packet delivery while packets are routed through multiple paths in the network, and [6] proposes a solution that supports in-order packet delivery under adaptive routing by reserving an alternate virtual path during the VC allocation process. Yet, such approaches are expensive to implement in terms of silicon footprint and have high power consumption due to the extensive use of buffers.…”

Section: Related Workmentioning

confidence: 99%

IPDeN: Real-Time deflection-based NoC with in-order flits delivery

Gonzalez

Nelissen

Tovar

2022

2022 IEEE 28th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

View full text Add to dashboard Cite

In deflection-based Network-on-Chips (NoC), when several flits entering a router contend for the same output port, one of the flits is routed to the desired output and the others are deflected to alternatives outputs. The approach reduces power consumption and silicon footprint in comparison to virtual channels (VCs) based solutions. However, due to the nondeterministic number of deflections that flits may suffer while traversing the network, flits may be received in an out-of-order fashion at their destinations. In this work, we present IPDeN, a novel deflectionbased NoC that ensures in-order flit delivery. To avoid the use of costly reordering mechanisms at the destination of each communication flow, we propose a solution based on a single small buffer added to each router to prevents flits from over taking other flits belonging to the same communication flow. We also develop a worst-case traversal time (WCTT) analysis for packets transmitted over IPDeN. We implemented IPDeN in Verilog and synthesized it for an FPGA platform. We show that a router of IPDeN requires "483-times less hardware resources than routers that use VCs. Experimental results shown that the worst-case and average packets communication time is reduced in comparison to the state-of-the-art

show abstract