Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs

Ho, Chun Hok; Leong, Philip H. W.; Luk, Wayne; Wilton, Steven J. E.; López-Buedo, Sergio

doi:10.1109/fccm.2006.71

Cited by 53 publications

(27 citation statements)

References 11 publications

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“…In our previous work [10], we compared an actual embedded multiplier with one modeled using the VEB method. It was found that timing difference can be as large as 11% while the area is accurately determined.…”

Section: B Veb Methodologymentioning

confidence: 99%

“…In earlier work, we described the VEB technique for modeling heterogeneous blocks using commercial tools [10], domain-specific hybrid FPGAs [11], and a word-based synthesizable FPGA architecture [12]. This paper provides a unified view of these studies, describes the proposed FPGA architecture in greater detail, presents improved results through the use of a higher performance commercial floating-point core, introduces the mapping process for the FPFPGA, discusses the requirement of a hardware compiler dedicated to such FPFPGA device, and includes two new synthetic benchmark circuits in the study, one of which is twice the size of the largest circuit studied previously.…”

Section: A Related Workmentioning

confidence: 99%

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Floating-Point FPGA: Architecture and Modeling

Leong

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point operations are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block scheme is proposed to model embedded blocks using existing field-programmable gate array (FPGA) tools. This methodology involves adopting existing FPGA resources to model the size, position, and delay of the embedded elements. The standard design flow offered by FPGA and computer-aided design vendors is then applied and static timing analysis can be used to estimate the performance of the FPGA with the embedded blocks. On selected floating-point benchmark circuits, our results indicate that the proposed architecture can achieve four times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.

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Section: B Veb Methodologymentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

Floating-Point FPGA: Architecture and Modeling

Leong

et al. 2009

IEEE Trans. VLSI Syst.

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“…We note that [99] suggests that larger gains from hard blocks can be obtained if a full re-timing pass is done on the circuit with the hard embedded blocks in place, particularly for highly pipelined circuits. The tool flow used to generate the data reported above did not use re-timing.…”

Section: Speed Gapmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

329

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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“…However, detailed constitution and area are not opened. Although [19] suggests the use of the LB area, the present study includes a routing region that has a large number of tracks. For this reason, we believe that a fair comparison can be made by using the standard cell information.…”

Section: Area and Delay Modelmentioning

confidence: 99%

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

Iida

Amagasaki

Okamoto

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYBecause of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

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Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs

Cited by 53 publications

References 11 publications

Floating-Point FPGA: Architecture and Modeling

Floating-Point FPGA: Architecture and Modeling

FPGA Architecture: Survey and Challenges

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization

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