Virtual memory window for application-specific reconfigurable coprocessors

Vuletic, M.; Pozzi, Laura; Ienne, Paolo

doi:10.1145/996566.996818

Cited by 18 publications

(14 citation statements)

References 19 publications

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“…It can be roughly classified into two non-disjunct sets: One set [12], [13], [25], [26], [27] already has fundamental limitations in individual requirements. The second one [12], [13], [14], [15], [29] implements only a subset of our functional requirements.…”

Section: Platform Requirementsmentioning

confidence: 99%

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Lange

Koch

2010

IEEE Trans. Comput.

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Abstract-We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23x times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89% of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility / performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.

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Section: Platform Requirementsmentioning

confidence: 99%

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Lange

Koch

2010

IEEE Trans. Comput.

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“…For systems with both hardware and software threads, migrating this processing off the CPU is critical, as significant overhead and jitter can be introduced if the CPU must be preempted in order to process OS requests for hardware threads being unblocked. In contrast, [23,24] reports a multithreaded capability that supports the creation and control of both hardware and software threads through Linux running on the CPU. This approach was taken to allow hardware threads to access data through Linux's existing virtual memory address space.…”

Section: Figure 2 Hthread Mutex Unlock Sequencementioning

confidence: 99%

Run-Time Services for Hybrid CPU/FPGA Systems on Chip

Agron

Peck

Anderson

et al. 2006

2006 27th IEEE International Real-Time Systems Symposium (RTSS'06)

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Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-programmable chip (MPSoPC) architectures. As researchers are investigating new methods for migrating portions of applications into custom hardware circuits, it is also critical to develop new run-time service frameworks to support these capabilities. Hthreads (HybridThreads) is a multithreaded RTOS kernel for hybrid FPGA/CPU systems designed to meet this new growing need. A key capability of hthreads is the migration of thread management, synchronization primitives, and run-time scheduling services for both hardware and software threads into hardware. This paper describes the hthreads scheduler, a key component for controlling both software-resident threads (SW threads) and threads implemented in programmable logic (HW threads). Run-time analysis shows that the hthreads scheduler module helps in reducing unwanted system overhead and jitter when compared to historical software schedulers, while fielding scheduling requests from both hardware and software threads in parallel with application execution. Run time analysis shows the scheduler achieves constant time scheduling for up to 256 active threads with a total of 128 different priority levels, while using uniform APIs for threads requesting OS services from either side of the hardware/software boundary.

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“…On our side, we concentrate on the unified memory space and seamless integration of SW and HW, thus the two approaches are complementary. Finally, a previous work [17] have introduced virtual memory for hardware accelerators but with limitations on parallel execution that we overcome in this paper.…”

Section: Related Workmentioning

confidence: 99%

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

Vuletic

Ienne

Claus

et al. 2006

2006 IEEE International Conference on Field Programmable Technology

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Abstract-Although naturally belonging to the user process, hardware parts of codesigned reconfigurable applications execute outside of the operating system (OS) process: they have neither unified memory abstraction with software nor system services provided by the OS. This imposes limitations on hardware and software interfacing, narrows available programming paradigms, and affects application portability. Advanced programming concepts, such as multithreading, usually demand additional activities on the programmer side, to perform memory transfers and enforce memory consistency. In this paper, we introduce a system layer (an OS extension relying on a system hardware extension) that provides: (1) unified virtual memory, (2) platform-agnostic interfacing, and (3) multithreaded execution, for hardware accelerators running within the same OS process with user software. The system layer releases software programmer and hardware designer from interfacing burdens and, still, achieves significant speedups over software with only limited overheads. Virtualmemory-enabled hardware accelerators benefit from all abstractions and services already available to software. To prove our concept in practice and demonstrate the ease of programming, we execute image processing and cryptography applications on reconfigurable systems-on-chip running GNU/Linux that supports virtual memory for multithreaded hardware accelerators.

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Virtual memory window for application-specific reconfigurable coprocessors

Cited by 18 publications

References 19 publications

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Run-Time Services for Hybrid CPU/FPGA Systems on Chip

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

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