Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

“…These overlays can then be combined with a host processor as a co-processor [10], [8], as in Fig. 6, with run-time management, including overlay configuration and data communication, being performed under OS [10] or hypervisor [9] control.…”

“…One possible solution is to treat the execution and management of software and hardware tasks in the same way, using a hypervisor or operating system (OS) such that the hardware fabric is viewed as just another software-managed task [7], [8]. This enables more shared use, while ensuring better isolation and predictability.…”

Throughput Oriented FPGA Overlays Using DSP Blocks

“…The Vivado HLS implementations of the replicated benchmarks require significantly less hardware resource (on average, our overlay requires 30× and 70× more slices, for benchmarks 1-12 and 13-24, respectively). However, this hardware penalty is the result of a general overlay architecture that can be effortlessly integrated into a virtualised hardware/software environment on the Zynq FPGA like the one in [4] that would incorporate both static and PR accelerators as well as overlays for generality and performance. The key advantage of an overlay is the fast compilation, software-like programmability and run-time management, with a relatively small configuration data size and fast non-preemptive hardware context switching, all of which are missing in a static Vivado HLS accelerator design.…”

“…Overlay architectures are an attractive solution for hardware acceleration of compute kernels on FPGAs because of their improved design productivity, by virtue of fast compilation, software-like programmability and run-time management, and high-level design abstraction [3], [4], [5], [6], [7], [8]. Other advantages include application portability across devices, better design reuse, and rapid reconfiguration that is orders of magnitude faster than partial reconfiguration on fine-grained FPGAs.…”

pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

“…Since 2007, many researchers (Dowty and Sugerman, 2009;Gupta et al, 2009;Shi et al, 2012;Giunta et al, 2010;Ravi et al, 2011;Lagar-Cavilla et al, 2007) have been focusing on making GPUs a shared resource within a virtualised environment, which would allow for adding GPUs to the infrastructure level of cloud computing. But the idea of adding FPGA accelerators to cloud computing (El-Araby et al, 2008;Gonzalez et al, 2012;Huang et al, 2010;Huang and Hsiung, 2013;Lübbers, 2010;Sabeghi and Bertels, 2009;Jain et al, 2014;Byma et al, 2014;Wang et al, 2013) still stays at an exploration stage.…”