VirtualRC

Kirchgessner, Robert; Stitt, Greg; George, Alan; Lam, Herman

doi:10.1145/2145694.2145728

Cited by 29 publications

(3 citation statements)

References 8 publications

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“…Primitives for FPGAs include sharing FPGA fabric [9,14,26,50,51,93], spatial multiplexing [15,28,84,91], context switch [59,77], memory virtualization [1,18,62,96], relocation [40], preemption [60], and interleaved hardware-software task execution [8,30,84,91]. Core techniques include virtualizing FPGA fabric, including regions [71], tasks [73], processing elements [21], IPC-like communication primitives [66], and abstraction layers/overlays [7,33,48,49,85] Extending OS abstractions to FPGAs is an area of active research. ReconOS [62] extends eCos [22] with hardware threads similar to Hthreads [70].…”

Section: Related Workmentioning

confidence: 99%

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Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3 − 4× of unvirtualized performance, and incur a modest increase in FPGA fabric utilization. CCS CONCEPTS• Hardware → Hardware description languages and compilation; Reconfigurable logic and FPGAs; • Software and its engineering → Compilers; Operating systems.

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Section: Related Workmentioning

confidence: 99%

“…FPGA compilation can be further improved with a virtualization layer. Overlay-based virtualization [7,42,48,49,52,95] abstracts away target-specific details and enables fast compilation and lower deployment latency. The approach reduces utilization and performance.…”

Section: Related Workmentioning

confidence: 99%

Compiler-driven FPGA virtualization with SYNERGY

Landgraf

Yang

Lin

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

View full text Add to dashboard Cite

show abstract

“…In [6] , a paravirtualized Xen Virtual Machine (VM) environment provides multiple-user services to access FPGA accelerators. Moreover, BORPH [7] is also a well known project working on UNIX interfaces for creating hardware-based drivers and providing FPGA hardware abstractions and management, while the VirtualRC platform [8] proposes a uniform hardware/software interface to access FPGAs. Moreover in [9] , authors have proposed the Object-Oriented Communication Engine (OOCE), a system-level middleware for FPGA-SoC heterogeneous architecture.…”

Section: Related Workmentioning

confidence: 99%