Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor

Abstract

To enable power-efficient object recognition of mobile intelligent robots, 81.6GOPS object recognition processor is proposed. Based on analysis of Scale Invariant Feature Transform (SIFT) algorithm, architecture of the proposed processor is designed to support both task and data level parallelism. 10 Processing Elements (PEs) are integrated for task parallelism, and each PE is equipped with SIMD instruction for data parallelism as well. In addition, Visual Image Processing memory replaces complex local maximum pixel search operation with a single read operation for further performance gain. With the proposed processor, we also realized vision platform for real-time SIFT computation of mobile robots. The chip operation is tested up to 200MHz and consumes 540mW in the vision platform at 1.8V supply voltage and 100 MHz operation frequency.

Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor

“…Most of stream applications consist of series of tasks which are feasible to organise as a task-level pipeline. Examples of such applications are MPEG-4 decoding [8], image depth extraction [7], object recognition [12] and many others. In the case of mapping such applications into multi-core processors, it is advantageous to assign different number of processing cores for each stage of the pipeline regarding the workloads.…”

“…Based on the idea described in Fig. 1b, we implemented a multi-core processor using the memory-centric NoC as an on-chip interconnection [10][11][12]. The architecture of the memory-centric NoC and the implemented processor is shown in Fig.…”