Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor

Kim, Dong-Hyun; Kim, Kwanho; Kim, Joo-Young; Lee, Seungjin; Yoo, Hoi‐Jun

doi:10.1049/iet-cdt.2008.0085

Cited by 8 publications

(1 citation statement)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The buffer circuits can be implemented using registers (flip-flops) or SRAM according to the buffer sizes. For large capacity queuing, the SRAM-based queuing buffer with separated read/write ports is preferred over a register-based buffer [17], [18]. However, SRAM incurs large latency overhead [10].…”

Section: Buffer Implementations and Architecturesmentioning

confidence: 99%

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

Huang

Hwang

2011

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip (SoC) designs. The buffer architecture and size, however, dominate the performance of OCINs and affect the design of routers. This work analyzes different buffer architectures and uses a data-link two-level FIFO (first-in first-out) buffer architecture to implement high-performance routers. The concepts of shared buffers and multiple accesses for buffers are developed using the two-level FIFO buffer architecture. The proposed two-level FIFO buffer architecture increases the utilities of the storage elements via the centralized buffer organization and reduces the area and power consumption of routers to achieve the same performance achieved by other buffer architectures. Depending on a cycleaccurate simulator, the proposed data-link two-level FIFO buffer can realize performance similar to that of the conventional virtual channels, while using 25% of the buffers. Consequently, the two-level FIFO buffer can achieve about 22% power reduction compared with the similar performance of the conventional virtual channels using UMC 65 nm CMOS technology. key words: two-level FIFO buffer, centralized shared buffer, router, on-chip interconnection network

show abstract

Section: Buffer Implementations and Architecturesmentioning

confidence: 99%