VLSI architecture for fast-recovery from NBTI in SRAM cell

A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM

“…As a result, interface traps at the Si/SiO2 interface and positive oxide charge in metal-oxide-silicon (MOS) are generated [21], then NBTI occurs. Consequently, a pMOS transistor will degrade with time for the NBTI effect, which results in the threshold voltage (V th ) of the pMOS increasing [20,21,22]. The V th variations will affect the speed and the channel resistance (R ds ) of a pMOS transistor [20].…”

“…Therefore, with an improvement in the reading speed and the continuous shrinking of CMOS process technology, the voltage difference between outp node and outn node can be enlarged for the NBTI effect at the beginning of the discharge [23]. Furthermore, the temperature and stress time will accelerate this degradation [22]. Consequently, the mismatch between the data branch and reference branch is increased, eventually leading to sense failure.…”

“…Then, the V th shift caused by the NBTI can be recovered, and the pMOS transistor is put into recovery mode [22]. According to several NBTI models proposed in references [24,25,26,27], the V th degradation is highly dependent on stress voltage (V SG ) and stress time (t).…”

“…Because the switching transistor P0 is turned off while "OUT-en" is logic "1", the V GS values of pre-charge transistors P1 and P2 in the proposed sense amplifier are smaller than that of conventional sensing circuits. Therefore, according to the NBTI recovery theory [22,26], the threshold voltage variation of pre-charge pMOS P1 and P2 will be reduced when the Negative Bias stress is decreased. Unfortunately, the proposed sense amplifier needs 3 added transistors, which result in an area overhead.…”