A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM

Abstract

STT-MRAM has been considered to be one of the most promising non-volatile memory candidates due its non-volatility, high speed, and unlimited endurance etc. However, with technology scaling down, STT-MRAM suffers from high sensitivity to process voltage and temperature (PVT) variations. Additionally, the negative bias temperature instability (NBTI) effect has become an important factor affecting the life of the pMOSFETs used in an STT-MRAM sense amplifier. Therefore, designing a more reliable sense amplifier has become a critical challenge. In this paper, a novel architecture for a sense amplifier is proposed, which includes switching transistors to decrease the NBTI effect on the pMOS device, and a balanced transistor to decrease the sensitivity of the sense amplifier to process variations.

A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design

“…In the modern technology area in not a major issue and production yield is decreasing due to complex chip fabrication process. The on-chip mitigation techniques help to increase the yield and life ot the chip [6]. Singh et al have proposed an oscillator frequency based NBTI sensor which collects the data from the test on-chip PMOS transistor for the specific stress mode [7].…”