VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design

Abstract

In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.

Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms

“…[20] and [21]. Their algorithms and architectures reduced the computation cycles by 50% compared with conventional architectures [5], [16], [19].…”

“…The cosine part is combined with 2 cos θ(k) on the left side of Fig. 2 after adopting the register-splitting schemes presented in [20] and [21]. The advantages of this technique are that it can increase speed and decrease power; thus, the maximum of the critical period is shortened to T m + 2T a less than in [5] and [17], where T m and T a are the time periods of the multiplier and adder, respectively.…”

“…For even points, the computational cycle of the proposed algorithm is 50.5% less than in [5], [17], and [19]. On the other hand, Yang and Chen [17] and Van et al [21] do not support the computation of odd-point DFT because the preprocessing unit divides the N -point input sequence by a factor of 2. In addition, Meher et al [22] divide the N -point input sequence into two summation terms by assuming M = N/2.…”

“…In addition, Meher et al [22] divide the N -point input sequence into two summation terms by assuming M = N/2. For critical period comparison, the proposed algorithm and Van et al [19], [21] taking one T m and two T a are shorter than those in [5] and [17]. For hardware costs, the proposed algorithm uses two multipliers and 13 adders, which are much smaller than others.…”

“…However, the critical periods of computation and computational cycles were larger than those of previous works, so Fan and Su [18] and Van and Yang [19] proposed a new method to reduce the limitations on its performance. To increase the efficiency of DFT and IDFT algorithms, Van et al proposed a highperformance and power-efficient very large scale integration (VLSI) algorithm and architecture [20], [21]. The DTMF application was provided using a hybrid of the input strength reduction scheme and Chebyshev's polynomial and registersplitting schemes.…”