Low-Cost and Shared Architecture Design of Recursive DFT/IDFT/IMDCT Algorithms for Digital Radio Mondiale System

High-performance RDFT design for applications of digital radio mondiale

“…To reduce the multiplication of in implementation, the coefficients of and 2 are decomposed by one multiplication and a simple shift operation. To reduce the usage of multipliers in implementation, a multiplier-sharing scheme is proposed in [2][3][4][19][20][21][22]. These multiplications of cosine and sine are computed by the same multiplier with one clock cycle delay in realization.…”

“…In case of PF-DFT algorithm, it is clearly known that there are no twiddle factors required by algorithm (5), and thus the multipliers of RDFT modules in the 1 st stage and 2 nd stage are only applied to process the computations of coefficient-free algorithm for the generation of cosine and sine in (2) individually. In case of CF-DFT algorithm, there are twiddle factors required by algorithm, and thus the multipliers of RDFT modules in the 2 nd stage are not only applied to process the generation of cosine and sine in (2) but also used to generate the twiddle factors. This increases the penalties of computational loading for modules #4 and #5 to execute the twiddle factors by coefficient-free algorithm.…”

“…On the other hand, it also adopted 1920 and 240-points IMDCT for AAC decoder. The computation of IMDCT could be converted into a recursive DFT (RDFT) kernel operation in Lai et al [2],which achieves lower computational complexity than some well-known recursive DCT-based designs [3,4]. Since the DFT can be used for computing the IMDCT, the transform length of IMDCT can be directly shortened from N into N/4.…”

“…Several fast DFT algorithms based on parallel designs and digital-signal-processing (DSP) processors [6][7][8][9][10] have been implemented and developed. To reduce the hardware costs, some recursive DFTs [11][12][13][14][15][16][17][18][19][20][21][22][23] and IMDCTs [2][3][4] have been suggested for an area-efficient design in implementation.…”

Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT) Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT) in a Digital Radio Mondiale (DRM) and DRM+ Receiver

“…However, it would be a great challenge to design a flexible FFT or IMDCT accelerator with the transform lengths of power-of-two and non-power-of-two. Currently, Lai et al [8] propose a recursive DFT (RDFT) to compute IMDCT coefficients. Due to the nature of recursive structure, Lai et al's hardware accelerator can arbitrarily switch transform length between power-of-two and non-power-of-two without any extra hardware processing units.…”