VLSI Architecture for the M Algorithm Suited for Detection and Source Coding Applications

VLSI implementation of SISO arithmetic decoders for joint source channel coding

“…Observing the results reported in Table 1, it is possible to see that the SMA requires a lower number of hardware resources than [9] and [11] methods, both when M = 128 and M = 256. However, the steps required to sort M numbers represented on 32 bit, using our method, is either greater than the numbers required by the [9] and [11] or lower than the number required by the [10] proposed architecture has been implemented in VHDL and synthesized using 0.13 µm CMOS standard cells technology. When M = 128 the number of equivalent gates required to realize the SISO AC is 1, 594, 088, whereas the amount of memory is 167kByte.…”

“…The Authors of [11] propose a simplified version of the algorithm described in [9] based on a different sorting strategies. In this case the selection phase needs two M − item odd-even sorting networks and one layer bitonic merge [3].…”

“…A straightforward comparison between the SISO AC and the architectures described in [9], [11] and [10] is impractical, due to the difference between the algorithms implemented. However, in Table 1 we have reported a compar- ison between the SMA and the MA proposed in [9], [11] and [10] in terms of number of comparators and steps required to select M paths with the highest value of metric.…”

“…However, in Table 1 we have reported a compar- ison between the SMA and the MA proposed in [9], [11] and [10] in terms of number of comparators and steps required to select M paths with the highest value of metric. Observing the results reported in Table 1, it is possible to see that the SMA requires a lower number of hardware resources than [9] and [11] methods, both when M = 128 and M = 256.…”

“…However, in Table 1 we have reported a compar- ison between the SMA and the MA proposed in [9], [11] and [10] in terms of number of comparators and steps required to select M paths with the highest value of metric. Observing the results reported in Table 1, it is possible to see that the SMA requires a lower number of hardware resources than [9] and [11] methods, both when M = 128 and M = 256. However, the steps required to sort M numbers represented on 32 bit, using our method, is either greater than the numbers required by the [9] and [11] or lower than the number required by the [10] proposed architecture has been implemented in VHDL and synthesized using 0.13 µm CMOS standard cells technology.…”