VLSI Design for High‐Precision Three‐Dimensional Depth Perception Chip

Abstract

This paper presents a Very large scale integration (VLSI) design method for Three‐dimensional (3D) depth perception chip based on infrared coding structure light. The primary sub‐modules on the chip contain the speckle pattern preprocessing module, block‐matching disparity estimation, depth mapping and post‐processing. The chip employs pipelining technology, and after Application specific integrated circuit (ASIC) verification, it proves that our chip has more advantages in performance of depth precision (12bits, 1mm @ 1m), image resolution (1280×960), time delay (less than 17ms), range limit (0.4~6m). It also can generate more stable and smooth depth map in real‐time, which can be used in 3D recognition, motion capture or scene perception.

Circuit Modeling and Performance Analysis of GNR@SWCNT Bundle Interconnects

“…With the continuous development of integrated circuit technology, the distributed resistance and capacitance of interconnects are constantly increasing, whereas the resistance-capacitance (RC) product of the transistors has been reduced [2]. As the length exceeds a certain value, the interconnect delay becomes much larger than the gate delay, implying that the integrated circuit has entered "the interconnect era" [3], [4].…”

“…In order to improve the electrical properties and reliability of traditional metal interconnects, carbon nan-otube (CNT) and graphene, which possess excellent properties including long mean free path (MFP), large relaxation time, high conductivity and high currentcarrying capacity [3], have been proposed as attractive candidates for constructing on-chip interconnects [5]- [10]. The resistance-inductance-capacitance (RLC) circuit models of on-chip interconnects made of single-walled CNT (SWCNT) bundle and multi-walled CNT have been studied in-depth, indicating that the CNT interconnects have better performance than Cu wires [11].…”