VLSI design of high speed Vedic Multiplier for FPGA implementation

Gavali, Kapil Ram; Kadam, Poonam

doi:10.1109/icetech.2016.7569385

Cited by 12 publications

(3 citation statements)

References 11 publications

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“…Srinivasan and Abdul Rajak have implemented physical level design by using IC compiler. The Vedic multipliers more efficient in terms of time delay, area, and power utilization in evaluation of conventional multiplier efficient for Vedic multipliers [17]. Again, in the same year Richa Sharma et.al have presented a propose of high-speed multiplier and squaring architectures by using Vedic mathematics sutras.…”

Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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The usual segmentation methods were addressed here: edge detection, clustering, and region growth. The problem with segmentation is that no one approach is suited for a certain type of picture, nor are all techniques applicable to all images. The importance of multiplication is rising according to the technology process. It is one of the major applications which is used in various domains such as business and digital signal process etc. The way of general multiplication is much more time taking process. So, mainly as to remove this time delay in this paper the concept of Vedic mathematics is introduced. This paper introduced about Indian ancient Vedic mathematics is involved to clear those problems. Sixteen sutras among the Vedic mathematics the one sutra that is widely used and implemented is “URDHVA-TIRYAGBHYAM” is proposed. The multiplication process of two 4 bit and two 3 bit and also two 2-bit multiplications are gone through this paper. This process ultimately leads to the consumption of less time and faster implementation. But, with respect to the order of multiplication, the complexity will also increase. When compared to other multipliers it takes less area.

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Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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“…VLSI circuits with high speed and minimal delay are a core part of this technological world. The performance and efficiency of a circuit are in the hands of adders and multipliers which is the deciding authority in VLSI design [1][2][3][4]. In carry select adder there is a trade-off between ripple carry adder and carry look ahead adder in area and delay [5].…”

Section: Introductionmentioning

confidence: 99%

Enhanced and Efficient Carry Select Adder with Minimal Delay

Srividhya¹,

Sivasakthi²,

Srivarshini³

et al. 2021

Advances in Parallel Computing

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In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

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“…Gavali and Kadam [10] introduced 11x8 bit multiplier using Vedic multiplier and implemented architecture using Xilinx ISE Design Suite 13.2 with Spartan 3E FPGA. They provided comparison of different Vedic multipliers in terms of speed and area.…”

Section: Fig2 Block Diagram Of 4×4 Bit Vedic Multiplier V a Review mentioning

confidence: 99%

High Speed Vedic Multiplier Based Review With Its Proposed Implementation for Parallel Fir Filter

2017

IJAERD

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VLSI design of high speed Vedic Multiplier for FPGA implementation

Cited by 12 publications

References 11 publications

Analysis of Multiplication Based on Vedic Mathematics

Analysis of Multiplication Based on Vedic Mathematics

Enhanced and Efficient Carry Select Adder with Minimal Delay

High Speed Vedic Multiplier Based Review With Its Proposed Implementation for Parallel Fir Filter

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