VLSI design synthesis with testability

Gebotys,; Elmasry,

doi:10.1109/dac.1988.14728

Cited by 25 publications

(3 citation statements)

References 8 publications

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“…[4][5][6][7][8][9] However, fewer probabilistic methods were reported. For example, Devadas 10 used a simulated annealing approach to solve the simultaneous cost/resource constrained allocation of functional units, registers, and interconnects by improving one solution at a time.…”

Section: Related Workmentioning

confidence: 99%

An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis

Harmanani

Saliba

2005

J CIRCUIT SYST COMP

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This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

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Section: Related Workmentioning

confidence: 99%

An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis

Harmanani

Saliba

2005

J CIRCUIT SYST COMP

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“…Highlevel data path synthesis is concerned with the automatic generation and allocation of registers, ALUs and buses. Many approaches to automated data path synthesis have been proposed in the literature [1][2][3][4][5][6][7][8][9][10][11][17][18][19][20][21][22]]. However, current high-level synthesis tools lack the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is not completely adequate for production use in comparison to manual design.…”

Section: Introductionmentioning

confidence: 99%

Using PDM on Multiport Memory Allocationin Data Path

Chen

1990

VLSI Design

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A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.

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“…Several approaches have been reported, varying from testability analysis [4,8,9,15] to testability method selecting [5,12,14,17,18,20,23]. A number of the proposed systems integrate DFT in a design in either a procedural fashion [3,10,21] or a knowledge-based one [1,2,6,7,11,13,16, 19,22]. However, these approaches have in common that they have at least one of the following disadvantages: operation at one design level, mostly the gate level, sometimes the RT level or the functional level.…”

Section: Motivation For Wagnermentioning

confidence: 99%

Integrating ASIC and board design-for-testability

Kraak

Proceedings Euro ASIC '92

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This paper presents the knowledge-based system WAG-NER that integrates the application of design-for-testability methods for boards, A S K S and boards containing ASICs. The system adapts the design to testing by using expert DFT knowledge and heuristics stored in a rulebase called TRISTAN and ISOLDE. T R I S m (TRI-Stage Testability ANalysis) qualitatively analyzes the testability of a circuit uniformly over the complete design hierarchy. It recognizes three design levels, i.e. the functional level, called block level, the RT or module level and the logic level. ISOLDE (Intelligent Synthesis Of testabLe DEsigns) synthesizes testability features on the basis of TRISTAN's analysis results at each design level, select-ing the most appropriate feature. A prototype implementation of the system in Prolog has been evaluated for several designs, showing the approach is feasible for automated testable design.

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VLSI design synthesis with testability

Cited by 25 publications

References 8 publications

An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis

An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis

Using PDM on Multiport Memory Allocationin Data Path

Integrating ASIC and board design-for-testability

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