VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality

Scholze, Stefan; Schiefer, Stefan; Partzsch, Johannes; Hartmann, Stephan; Mayr, Christian; Höppner, Sebastian; Eisenreich, Holger; Henker, Stephan; Vogginger, Bernhard; Schüffny, René

doi:10.3389/fnins.2011.00117

Cited by 36 publications

(20 citation statements)

References 26 publications

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“…An automated mapping process translates the description into the detailed configuration that is written to the wafer-modules (Wendt et al, 2008; Ehrlich et al, 2010). These modules are interconnected by a high-speed network to communicate spike-events (Scholze et al, 2011). External stimulation can be applied to the network from the control cluster, using the high-speed links that are also used for configuration.…”

Section: Methodsmentioning

confidence: 99%

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

Friedmann¹,

Frémaux²,

Schemmel³

et al. 2013

Front. Neurosci.

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In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project.

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Section: Methodsmentioning

confidence: 99%

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

Friedmann¹,

Frémaux²,

Schemmel³

et al. 2013

Front. Neurosci.

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“…The first problem, that of developing real-time interfaces between the different AER chips to create complex multi-chip systems, is currently being addressed by developing both custom real-time hardware solutions (Gomez-Rodriguez et al, 2006; Fasnacht et al, 2008; Hofstaetter et al, 2010; Jin et al, 2010; Fasnacht and Indiveri, 2011; Scholze et al, 2011), as well as software solutions, and principled systematic methods for configuring network structures and system parameters (Davison et al, 2008; Neftci et al, 2011, 2012; Sheik et al, 2011). …”

Section: Introductionmentioning

confidence: 99%

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System

Sheik¹,

Coath²,

Indiveri³

et al. 2012

Front. Neurosci.

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Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

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“…In addition, implementing the virtual tree requires memory lookups enroute, resulting in longer latencies. FACETS [42] (a twolevel network with degrees 9 and 6) and HiAER [43] (a twolevel network with degrees 2 and 5) use a hierarchal topology but are not guaranteed to be deadlock-free because branching is allowed on the upward path. Hardware measurements of throughput versus latency were not available from any of these systems for comparison at the time of publication.…”

Section: Discussionmentioning

confidence: 99%

A Multicast Tree Router for Multichip Neuromorphic Systems

Merolla

Arthur

Alvarez

et al. 2014

IEEE Trans. Circuits Syst. I

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Abstract-We present a tree router for multichip systems that guarantees deadlock-free multicast packet routing without dropping packets or restricting their length. Multicast routing is required to efficiently connect massively parallel systems' computational units when each unit is connected to thousands of others residing on multiple chips, which is the case in neuromorphic systems. Our tree router implements this one-tomany routing by branching recursively-broadcasting the packet within a specified subtree. Within this subtree, the packet is only accepted by chips that have been programmed to do so. This approach boosts throughput because memory look-ups are avoided enroute, and keeps the header compact because it only specifies the route to the subtree's root. Deadlock is avoided by routing in two phases-an upward phase and a downward phase-and by restricting branching to the downward phase. This design is the first fully implemented wormhole router with packet-branching that can never deadlock. The design's effectiveness is demonstrated in Neurogrid, a million-neuron neuromorphic system consisting of sixteen chips. Each chip has a 256×256 silicon-neuron array integrated with a full-custom asynchronous VLSI implementation of the router that delivers up to 1.17G words/s across the sixteen-chip network with less than 1µs jitter.

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VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality

Cited by 36 publications

References 26 publications

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System

A Multicast Tree Router for Multichip Neuromorphic Systems

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