Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)
DOI: 10.1109/asic.2001.954663
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VLSI implementation of high performance burst mode for 128-bit block ciphers

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Cited by 6 publications
(18 citation statements)
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“…The verifications for all the configurations, the throughput can be ranged between 1.59 and 2.25 Gbps with the hardware cost of 0.54 and 3.92 mm2. Comparing with the existing designs [10][11][12][13][14], the performance of proposed design is better than the others in terms of the evaluation index DRPA. Obviously, with the provided high security, the proposed high performance IP is easily integrated for most of the requirement in high quality real-time multimedia applications with acceptable hardware cost.…”
Section: Introductionmentioning
confidence: 90%
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“…The verifications for all the configurations, the throughput can be ranged between 1.59 and 2.25 Gbps with the hardware cost of 0.54 and 3.92 mm2. Comparing with the existing designs [10][11][12][13][14], the performance of proposed design is better than the others in terms of the evaluation index DRPA. Obviously, with the provided high security, the proposed high performance IP is easily integrated for most of the requirement in high quality real-time multimedia applications with acceptable hardware cost.…”
Section: Introductionmentioning
confidence: 90%
“…They are defined as follows: 8,4), (1,9,5), (2,10,6), (3,11,7), (4,12,8), (5,13,9), (6,14,10), (7, 15, …”
Section: The Proposed Cryptographic System 21 Multimedia Cryptographmentioning
confidence: 99%
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