VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

A 16-Bit High-Speed Multiplier Design Based on Karatsuba Algorithm and Urdhva-Tiryagbhyam Theorem Using Modified Gdi Cells for Low Power and Area Constraints

“…The design techniques followed for a multiplier based on the UT theorem have been described in [6] and [7]. The use of the GDI technology for various logical circuits has been presented in [8].…”