VLSI logic and fault simulation on general-purpose parallel computers

Mueller-Thuns, R.B.; Saab, D.G.; Damiano, Robert; Abraham, Jacob A.

doi:10.1109/43.215006

Cited by 56 publications

(20 citation statements)

References 33 publications

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“…Algorithm-parallel efforts aim at parallelizing the fault simulation algorithm, distributing workload and/or pipelining the tasks, such that the frequency of communication and synchronization between processors is reduced [14,2,3,4]. In contrast to these approaches, our approach is data-parallel.…”

Section: Previous Workmentioning

confidence: 99%

“…In contrast to these approaches, our approach is data-parallel. In [14], the authors aim at heuristically assigning fault set partitions (and corresponding circuit partitions) to several medium-grain multiprocessors. This assignment is based on a performance model developed by comparing the communication (message passing or shared memory access) to computation ratio of the multiprocessor units.…”

Section: Previous Workmentioning

confidence: 99%

“…Fault simulation can be parallelized by a variety of techniques. The techniques include parallelizing the fault simulation algorithm (algorithm-parallel techniques [2,3,4]), par-titioning the circuit into disjoint components and simulating them in parallel (model-parallel techniques [5,6]), partitioning the fault set data and simulating faults in parallel (data-parallel techniques [7,8,9,10,11,12,13]) and a combination of one or more of these techniques [14]. Data parallel techniques can be further classified into fault-parallel methods, wherein different faults are simulated in parallel, and pattern-parallel approaches, wherein different patterns of the same fault are simulated in parallel.…”

Section: Introductionmentioning

confidence: 99%

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Towards acceleration of fault simulation using graphics processing units

Gulati

Khatri

2008

Proceedings of the 45th Annual Design Automation Conference

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In this paper, we explore the implementation of fault simulation on a Graphics Processing Unit (GPU). In particular, we implement a fault simulator that exploits thread level parallelism. Fault simulation is inherently parallelizable, and the large number of threads that can be computed in parallel on a GPU results in a natural fit for the problem of fault simulation. Our implementation faultsimulates all the gates in a particular level of a circuit, including good and faulty circuit simulations, for all patterns, in parallel. Since GPUs have an extremely large memory bandwidth, we implement each of our fault simulation threads (which execute in parallel with no data dependencies) using memory lookup. Fault injection is also done along with gate evaluation, with each thread using a different fault injection mask. All threads compute identical instructions, but on different data, as required by the Single Instruction Multiple Data (SIMD) programming semantics of the GPU. Our results, implemented on a NVIDIA GeForce GTX 8800 GPU card, indicate that our approach is on average 35× faster when compared to a commercial fault simulation engine. With the recently announced Tesla GPU servers housing up to eight GPUs, our approach would be potentially 238× faster. The correctness of the GPU based fault simulator has been verified by comparing its result with a CPU based fault simulator.

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Towards acceleration of fault simulation using graphics processing units

Gulati

Khatri

2008

Proceedings of the 45th Annual Design Automation Conference

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“…1) Fault list partitioning [1], [2]. In this approach, a complete list of faults F is partitioned into several sub lists n F F F ,..., , 2 1 , each of which is transferred to a separate processor in system, where fault simulation on a given test sequence is performed.…”

Section: Introductionmentioning

confidence: 99%

Parallel Simulation Algorithm of VLSI for Multicore Workstations with Dynamic Faults Grouping

Ivanov¹

2016

IJMO

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Abstract-A new algorithm for parallel fault simulation of VLSI on multicore workstations with common memory is proposed. To speeding up the algorithm two-level parallelization is used. First, main schema of the algorithm is based on the concurrent many-threaded simulation of the groups of faults for each input vector. Second, each group of faults is simulated in bit-parallel way. The dynamic fault grouping is adopted. The results of computational experiments on ISCAS-89 benchmarks circuits are reported, which are obtained on the 12-core workstation.

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“…As a basic assumption, the process of the evaluation of combinational logic during the parallel simulation of a cycle has to be left unchanged. Therefore [5,13] satis¯es the following conditions: Therefore, we are forced to de¯ne basic units for partitioning which are known as cones [12,6,7] The fan-out…”

Section: Introductionmentioning

confidence: 99%