Void Formation and Their Effect on Reliability of Lead-Free Solder Joints on MID and PCB Substrates

Wild, Paul; Grözinger, Tobias; Lorenz, Dominik; Zimmermann, André

doi:10.1109/tr.2017.2759231

Cited by 24 publications

(9 citation statements)

References 9 publications

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“…However, thermal management has been identified as the main barrier for further power density increase [4]. The heat generated inside the miniaturized semiconductors must be effectively dissipated to the ambient; otherwise, the high junction and board temperatures may cause serious reliability issues to the semiconductor, solder, thermal grease, and printed circuit board (PCB) [5]- [8]. In addition, suitable heat dissipation measures should be considered as early as in the design and development phase, because subsequent modifications are generally more costly and involve increased engineering effort [9], [10].…”

Section: Kcumentioning

confidence: 99%

“…The terms "Series", "D-Y" and "Cross" represent the series transformation, D-Y transformation, and cross transformation of resistor network, respectively. (8) where i represents the copper layer order, and j denotes the outer via layer order. Meanwhile, it is observed from (8) that both the radial and vertical outer-zone thermal resistances are functions of j, implying the two types of thermal resistances vary with respect to the outer via layer number.…”

Section: ) Lumped Thermal Resistance Modelmentioning

confidence: 99%

“…The equivalent thermal resistance of the complicated network shown in Fig. 5(c) can be derived by performing analog circuit simulations with given radial and vertical thermal resistance values as (8). However, there are multiple design variables (e.g., , s, j) and system parameters (l, w, tCu, kfiller, tPTH, NCu, t), which implies that the method of circuit simulation does not support systematical parametric analysis.…”

Section: ) Derivation Of Equivalent Thermal Resistancementioning

confidence: 99%

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Thermal Modeling and Design Optimization of PCB Vias and Pads

Shen

Wang

Blaabjerg

et al. 2020

IEEE Trans. Power Electron.

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Miniature power semiconductor devices mounted on printed circuit boards (PCBs) are normally cooled by means of PCB vias, copper pads, and/or heatsinks. Various reference PCB thermal designs have been provided by semiconductor manufacturers and researchers. However, the recommendations are not optimal, and there are some discrepancies among them, which may confuse electrical engineers. This paper aims to develop analytical thermal resistance models for PCB vias and pads, and further to obtain the optimal design for thermal resistance minimization. Firstly, the PCB via array is thermally modeled in terms of multiple design parameters. A systematic parametric analysis leads to an optimal trajectory for the via diameter at different PCB specifications. Then an axisymmetric thermal resistance model is developed for PCB thermal pads where the heat conduction, convection and radiation all exist; due to the interdependence between the conductive/radiative heat transfer coefficients and the board temperatures, an algorithm is proposed to fast obtain the board-ambient thermal resistance and to predict the semiconductor junction temperature. Finally, the proposed thermal models and design optimization algorithms are verified by computational fluid dynamics (CFD) simulations and experimental measurements. Index terms-thermal resistance model, thermal management, printed circuit board (PCB), PCB via, thermal pad. NOMENCLATURE Bi Biot number h Heat transfer coefficient (W/(m 2 •K)) hconv Convective heat transfer coefficient (W/(m 2 •K)) hradi Radiative heat transfer coefficient (W/(m 2 •K)) k Thermal conductivity of a material (W/(m•K)) k1 Lateral thermal conductivity of the copper zone (W/(m 2 •K)) k2 Lateral thermal conductivity of the FR4 zone (W/(m 2 •K))

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Section: Kcumentioning

confidence: 99%

Section: ) Lumped Thermal Resistance Modelmentioning

confidence: 99%

Section: ) Derivation Of Equivalent Thermal Resistancementioning

confidence: 99%

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Thermal Modeling and Design Optimization of PCB Vias and Pads

Shen

Wang

Blaabjerg

et al. 2020

IEEE Trans. Power Electron.

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“…The electron microscope has permitted the study of the inner cross-section of MOSFET for modelling via finite volume simulation and the voids effects inside the solder joints can be correlated to the common approach of effective thermal conductivity (Fladischer et al, 2018). Actually, there are studies for avoiding the voids on Power MOSFET's as well as the methods for the optimization of the join soldiers and the procedures for their evaluation (Tran et al, 2017b;Wild et al, 2017).…”

Section: Introductionmentioning

confidence: 99%

Inspección no destructiva de vacíos en MOSFET de Potencia

2019

NOVASINERGIA

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Los vacíos pueden afectar la función normal de los transistores de efecto de campo Metal-Oxide-Semiconductor (MOSFET) si son más del 25 % del área total, siendo esta una característica importante en el control de calidad de los vacíos en el proceso de fabricación. El método experimental se empleó utilizando la microscopía electrónica de barrido con espectroscopia de dispersión de energía (SEM-EDS) y la técnica de microtomografía. El método de microscopía electrónica de barrido con espectroscopia de dispersión de energía permitió la cuantificación de las características químicas y físicas de la capa de soldadura en cada dispositivo. El método de microtomografía se ha utilizado como método de inspección no destructiva (NDI) en los MOSFET de potencia para cuantificar los huecos. La metodología de investigación permitió la cuantificación de los vacíos con el objetivo de inspeccionar las imperfecciones de fabricación que influyen en el rendimiento del dispositivo. La programación orientada a objetos se desarrolló utilizando el software LabView que permite mejorar la detección de huecos desde una imagen con distorsión, cuantificar microvoides y macrovoides, la ubicación en la capa de soldadura utilizando el centro de masa de vaciado y su resultado estadístico. Los resultados del análisis de vacíos demostraron que la técnica y los métodos utilizados para este tipo de detección de defectos en Power MOSFET podrían representar una herramienta NDI adecuada para el control de calidad.

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“…Several studies consider the thermal performance of LEDs on MIDs [16][17][18][19][20] by investigating the effects of different heat dissipation concepts on the heating of the p-n junction. Other studies focus on the reliability of surface mounted devices (SMD) on MIDs under thermal cyclic testing with respect to the thermomechanical behavior and the void formation in the solder joints [21][22][23]. However, as mentioned before, no detailed investigations about the long-term behavior of LEDs on MIDs and, consequently, about their lifetime relating to the effect of the substrate material were conducted.…”

Section: Introductionmentioning

confidence: 99%

Development and Validation of a Novel Setup for LEDs Lifetime Estimation on Molded Interconnect Devices

et al. 2018

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Higher energy efficiency, more compact design, and longer lifetime of light-emitting diodes (LEDs) have resulted in increasing their market share in the lighting industry, especially in the industries of consumer electronics, automotive, and general lighting. Due to their robustness and reliability, LEDs have replaced conventional light sources, such as fluorescent lamps. Many studies are examining the reliability of LEDs as such or investigating their long-term behavior on standard printed circuit boards (PCB). However, the thermal performance of LEDs mounted on nonconventional substrates is still not explored enough. An interesting example for this is the molded interconnect devices (MID), which are well known for the great design freedom and the great potential for functional integration. These characteristics not only underline the main abilities of the MID technology, but also present some challenges concerning thermal management. The long-term behavior of LEDs on MID is still quite untapped and this prevents this technology from consolidating its existence. In this context, this work highlights a developed test setup aimed at investigating LEDs, mounted on molded interconnect devices, under combined stress conditions. The results of the reliability study, as well as the resulting lifetime model, are also illustrated and discussed.

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Void Formation and Their Effect on Reliability of Lead-Free Solder Joints on MID and PCB Substrates

Cited by 24 publications

References 9 publications

Thermal Modeling and Design Optimization of PCB Vias and Pads

Thermal Modeling and Design Optimization of PCB Vias and Pads

Inspección no destructiva de vacíos en MOSFET de Potencia

Development and Validation of a Novel Setup for LEDs Lifetime Estimation on Molded Interconnect Devices

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