Volatile and Nonvolatile Memory Operations Implemented in a Pt/HfO₂/Ti Memristor

Wu, Lei; Liu, Hongxia; Lin, Jian-Yang; Wang, Shulong

doi:10.1109/ted.2021.3061033

Cited by 30 publications

(11 citation statements)

References 32 publications

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“…Furthermore, it is found that combing a volatile and non‐volatile memristor in an artificial synapse provides an efficient way to improve the learning in spiking neural networks. [ 12 ] Therefore, electronic devices incorporating both volatility and non‐volatility are of great significance for the realization of more neural networks. [ 8 ] Fortunately, ion migration in metal‐filament‐based memristors is quite similar to the information‐transport process in realistic biological synapses.…”

Section: Introductionmentioning

confidence: 99%

“…Indeed, both the volatile and non-volatile electronic memories have been widely adopted in neuromorphic systems. For example, analogue to the forgetting property of human brain, the volatile memories including threshold switching memristors are usually used to mimic the synaptic STP of synapse, [12] or implement the leaky integrate and fire function of neuron. [13] In addition, the non-volatile memories, such as resistance random access memory, [14,15] phase change memory, [16,17] ferroelectric tunneling junction, [18,19] and floating gate transistor, [20] can simulate the LTP of synapse well.…”

Section: Introductionmentioning

confidence: 99%

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Mimicking Neuroplasticity via Ion Migration in van der Waals Layered Copper Indium Thiophosphate

et al. 2021

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Device Fabrication and Measurement: Standard photolithography process was performed to pattern the electrodes, which were then followed by deposition of 8/30 nm Cr/Au films using an electron beam evaporator. The electrical characterization was performed by FS-Pro 380 semiconductor device analyzer with devices placed in a vacuum probe station. For the temperature-dependent tests, devices were placed on a Linkam THMS350V stage.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mimicking Neuroplasticity via Ion Migration in van der Waals Layered Copper Indium Thiophosphate

et al. 2021

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“…In biological synapses, two types of synaptic plasticity, namely long-term plasticity (LTP) and short-term plasticity (STP; Kandel, 2000;Martin et al, 2000), are observed. Kim et al (2015), Li et al (2013), Mannan et al (2021), Wang et al (2017), Wu et al (2021), Zhang et al (2017), Yang et al (2018), and Ren et al (2018) constructed mem-ristors to emulate both long-term plasticity (LTP) and shortterm plasticity (STP) adaptation functions of the synapses.…”

Section: Introductionmentioning

confidence: 99%

Design of a CMOS memristor emulator-based, self-adaptive spiking analog-to-digital data conversion as the lowest level of a self-x hierarchy

Abd

König

2022

J. Sens. Sens. Syst.

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Abstract. The number of sensors used in modern devices is rapidly increasing, and the interaction with sensors demands analog-to-digital data conversion (ADC). A conventional ADC in leading-edge technologies faces many issues due to signal swings, manufacturing deviations, noise, etc. Designers of ADCs are moving to the time domain and digital designs techniques to deal with these issues. This work pursues a novel self-adaptive spiking neural ADC (SN-ADC) design with promising features, e.g., technology scaling issues, low-voltage operation, low power, and noise-robust conditioning. The SN-ADC uses spike time to carry the information. Therefore, it can be effectively translated to aggressive new technologies to implement reliable advanced sensory electronic systems. The SN-ADC supports self-x (self-calibration, self-optimization, and self-healing) and machine learning required for the internet of things (IoT) and Industry 4.0. We have designed the main part of SN-ADC, which is an adaptive spike-to-digital converter (ASDC). The ASDC is based on a self-adaptive complementary metal–oxide–semiconductor (CMOS) memristor. It mimics the functionality of biological synapses, long-term plasticity, and short-term plasticity. The key advantage of our design is the entirely local unsupervised adaptation scheme. The adaptation scheme consists of two hierarchical layers; the first layer is self-adapted, and the second layer is manually treated in this work. In our previous work, the adaptation process is based on 96 variables. Therefore, it requires considerable adaptation time to correct the synapses' weight. This paper proposes a novel self-adaptive scheme to reduce the number of variables to only four and has better adaptation capability with less delay time than our previous implementation. The maximum adaptation times of our previous work and this work are 15 h and 27 min vs. 1 min and 47.3 s. The current winner-take-all (WTA) circuits have issues, a high-cost design, and no identifying the close spikes. Therefore, a novel WTA circuit with memory is proposed. It used 352 transistors for 16 inputs and can process spikes with a minimum time difference of 3 ns. The ASDC has been tested under static and dynamic variations. The nominal values of the SN-ADC parameters' number of missing codes (NOMCs), integral non-linearity (INL), and differential non-linearity (DNL) are no missing code, 0.4 and 0.22 LSB, respectively, where LSB stands for the least significant bit. However, these values are degraded due to the dynamic and static deviation with maximum simulated change equal to 0.88 and 4 LSB and 6 codes for DNL, INL, and NOMC, respectively. The adaptation resets the SN-ADC parameters to the nominal values. The proposed ASDC is designed using X-FAB 0.35 µm CMOS technology and Cadence tools.

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“…Gradual memristors have many limitations in endurance, retention, and conductivity range compared with abrupt switching memristors but have better conductivity linearity. [16][17][18][19] These deficiencies affect the reliability and pattern recognition accuracy for the Modified National Institute of Standards and Technology (MNIST) classification. [20][21][22][23] The weight distance between each conductance increases owing to sufficient conductance states.…”

Section: Introductionmentioning

confidence: 99%

Mechanism and Conductance Range Enhancement of TiN/AlO_x/AlO_y/ITO Synaptic Devices

Zhang

Zhao

et al. 2022

Physica Rapid Research Ltrs

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Enhancement of the conductance range of memristors used in synaptic devices is essential for achieving high‐performance neural networks. Herein, a memristor based on the stack structure of TiN/AlO x /AlO y /ITO is designed to enhance the conductance range. The AlO x /AlO y devices exhibit pseudointerface switching characteristics with higher switching ratios and reliability under a compliance current of 1 mA. The high‐resistance state/low‐resistance state ratio of the AlO x /AlO y devices increases from 11.4 to 128.6 compared with the AlO x devices. Accompanied by high‐conductance linearity, the conductance range increases from 36–202 to 25–280 μS simultaneously. Based on the related electrical properties and microstructure analysis, the regulation mechanism of the formation and rupture of conductive filaments by the oxygen concentration gradient is demonstrated. Simulations using the Modified National Institute of Standards and Technology (MNIST) handwritten recognition data set prove that the AlO x /AlO y memristor can operate with a learning accuracy of 91.07%.

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Volatile and Nonvolatile Memory Operations Implemented in a Pt/HfO₂/Ti Memristor

Cited by 30 publications

References 32 publications

Mimicking Neuroplasticity via Ion Migration in van der Waals Layered Copper Indium Thiophosphate

Mimicking Neuroplasticity via Ion Migration in van der Waals Layered Copper Indium Thiophosphate

Design of a CMOS memristor emulator-based, self-adaptive spiking analog-to-digital data conversion as the lowest level of a self-x hierarchy

Mechanism and Conductance Range Enhancement of TiN/AlO_x/AlO_y/ITO Synaptic Devices

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Volatile and Nonvolatile Memory Operations Implemented in a Pt/HfO₂/Ti Memristor

Cited by 30 publications

References 32 publications

Mimicking Neuroplasticity via Ion Migration in van der Waals Layered Copper Indium Thiophosphate

Mimicking Neuroplasticity via Ion Migration in van der Waals Layered Copper Indium Thiophosphate

Design of a CMOS memristor emulator-based, self-adaptive spiking analog-to-digital data conversion as the lowest level of a self-x hierarchy

Mechanism and Conductance Range Enhancement of TiN/AlOx/AlOy/ITO Synaptic Devices

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Mechanism and Conductance Range Enhancement of TiN/AlO_x/AlO_y/ITO Synaptic Devices