Voltage-Driven Building Block for Hardware Belief Networks

Hassan, Orchi; Datta, Supriyo

doi:10.1109/mdat.2019.2897964

Cited by 17 publications

(13 citation statements)

References 11 publications

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“…1 receives its input from a weighted sum of other BSN's obtained from a "synapse" I i (n) = j W ij m j (n). A wide variety of functions can be implemented by properly designing or learning the weights W ij [8]- [10]. The BSN function (Eq.…”

Section: Introductionmentioning

confidence: 99%

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

et al. 2019

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Binary stochastic neurons (BSN's) form an integral part of many machine learning algorithms, motivating the development of hardware accelerators for this complex function. It has been recognized that hardware BSN's can be implemented using low barrier magnets (LBM's) by minimally modifying presentday magnetoresistive random access memory (MRAM) devices. A crucial parameter that determines the response of these LBM based BSN designs is the correlation time of magnetization, τc. In this letter, we show that for magnets with low energy barriers (∆ ≈ kBT and below), circular disk magnets with inplane magnetic anisotropy (IMA) lead to τc values that are two orders of magnitude smaller compared to τc for magnets having perpendicular magnetic anisotropy (PMA) and provide analytical descriptions. We show that this striking difference in τc is due to a precession-like fluctuation mechanism that is enabled by the large demagnetization field in IMA magnets. We provide a detailed energy-delay performance evaluation of previously proposed BSN designs based on Spin-Orbit-Torque (SOT) MRAM and Spin-Transfer-Torque (STT) MRAM employing low barrier circular IMA magnets by SPICE simulations. The designs exhibit sub-ns response times leading to energy requirements of ∼a few fJ to evaluate the BSN function, orders of magnitude lower than digital CMOS implementations with a much larger footprint. While modern MRAM technology is based on PMA magnets, results in this paper suggest that low barrier circular IMA magnets may be more suitable for this application.Index Terms-Binary stochastic neuron, hardware implementation, low barrier magnet, embedded MTJ, probabilistic computing

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Section: Introductionmentioning

confidence: 99%

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

et al. 2019

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“…Unstable nanomagnet based spintronic devices have recently attracted much research interest for probabilistic spin logic (PSL) [10][11][12][13][14][15][16][17][18][19][20][21][22] and are given the name "p-bit", which is the short form of "probabilistic bit". It has been proposed that inherently unstable nanomagnet can be a natural implementation of the stochastic variable in a BN 10,19,20,23 . We first present a p-bit implementation using a stochastic spintronic device that has isolated input and output to allow for interconnection in circuitry.…”

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confidence: 99%

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

Debashis

Ostwal

Faria

et al. 2020

Sci Rep

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Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the stochastic variables in a Bayesian network that encode the probability of occurrence of the associated event. This work presents an experimental demonstration of a Bayesian network building block implemented with inherently stochastic spintronic devices based on the natural physics of nanomagnets. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.

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“…Note that the control of weights through C ij works best if C 0 j C ij so that W i,j ≈ C i,j /C 0 , however it is possible to design a weighted p-bit design without this assumption (C 0 C ij ) as discussed in detail in Ref. 52 . Similar control can also be achieved through a network of resistors.…”

Section: B Weighted P-bitmentioning

confidence: 99%

p-bits for probabilistic spin logic

Çamsarı

Sutton

Datta

2019

Applied Physics Reviews

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156

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We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. We show that low barrier magnets or LBM's provide a natural physical representation for p-bits and can be built either from perpendicular magnets (PMA) designed to be close to the in-plane transition or from circular in-plane magnets (IMA). Magnetic tunnel junctions (MTJ) built using LBM's as free layers can be combined with standard NMOS transistors to provide threeterminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded MRAM technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ, any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology. CONTENTS

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Voltage-Driven Building Block for Hardware Belief Networks

Cited by 17 publications

References 11 publications

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

Low-Barrier Magnet Design for Efficient Hardware Binary Stochastic Neurons

Hardware implementation of Bayesian network building blocks with stochastic spintronic devices

p-bits for probabilistic spin logic

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