Binary stochastic neurons (BSN's) form an integral part of many machine learning algorithms, motivating the development of hardware accelerators for this complex function. It has been recognized that hardware BSN's can be implemented using low barrier magnets (LBM's) by minimally modifying presentday magnetoresistive random access memory (MRAM) devices. A crucial parameter that determines the response of these LBM based BSN designs is the correlation time of magnetization, τc. In this letter, we show that for magnets with low energy barriers (∆ ≈ kBT and below), circular disk magnets with inplane magnetic anisotropy (IMA) lead to τc values that are two orders of magnitude smaller compared to τc for magnets having perpendicular magnetic anisotropy (PMA) and provide analytical descriptions. We show that this striking difference in τc is due to a precession-like fluctuation mechanism that is enabled by the large demagnetization field in IMA magnets. We provide a detailed energy-delay performance evaluation of previously proposed BSN designs based on Spin-Orbit-Torque (SOT) MRAM and Spin-Transfer-Torque (STT) MRAM employing low barrier circular IMA magnets by SPICE simulations. The designs exhibit sub-ns response times leading to energy requirements of ∼a few fJ to evaluate the BSN function, orders of magnitude lower than digital CMOS implementations with a much larger footprint. While modern MRAM technology is based on PMA magnets, results in this paper suggest that low barrier circular IMA magnets may be more suitable for this application.Index Terms-Binary stochastic neuron, hardware implementation, low barrier magnet, embedded MTJ, probabilistic computing

We describe an equivalent circuit model applicable to a wide variety of magnetoelectric phenomena and use SPICE simulations to benchmark this model against experimental data. We use this model to suggest a different mode of operation where the "1" and "0" states are not represented by states with net magnetization (like mx, my or mz) but by different easy axes, quantitatively described by (m 2x − m 2 y ) which switches from "0" to "1" through the write voltage. This change is directly detected as a read signal through the inverse effect. The use of (m 2x − m 2 y ) to represent a bit is a radical departure from the standard convention of using the magnetization (m) to represent information. We then show how the equivalent circuit can be used to build a device exhibiting tunable randomness and suggest possibilities for extending it to non-volatile memory with read and write capabilities, without the use of external magnetic fields or magnetic tunnel junctions.

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Probabilistic spin logic (PSL) based on networks of binary stochastic neurons (or p-bits) has been shown to provide a viable framework for many functionalities including Ising computing, Bayesian inference, invertible Boolean logic and image recognition. This paper presents a hardware building block for the PSL architecture, consisting of an embedded MTJ and a capacitive voltage adder of the type used in neuMOS. We use SPICE simulations to show how identical copies of these building blocks (or weighted p-bits) can be interconnected with wires to design and solve a small instance of the NP-complete Subset Sum Problem fully in hardware.

Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to build an Ising spin, or a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a low-barrier nanomagnet based design that uses a single magnetic tunnel junction (MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic resistor (1SR). Such a compact unit can drastically reduce the area footprint of BSNs while promising massive scalability by leveraging the existing Magnetic RAM (MRAM) technology that has integrated 1T-1MTJ cells in ∼ Gbit densities. The 3T-1SR design however can be realized using different materials or devices that provide naturally fluctuating resistances. Extending previous work, we evaluate hardware BSNs from this general perspective by classifying necessary and sufficient conditions to design a fast and energy-efficient BSN that can be used in scaled Ising Machine implementations. We connect our device analysis to systems-level metrics by emphasizing hardware-independent figures-of-merit such as flips per second and dissipated energy per random bit that can be used to classify any Ising Machine.