2021
DOI: 10.1103/physrevapplied.15.064046
|View full text |Cite
|
Sign up to set email alerts
|

Quantitative Evaluation of Hardware Binary Stochastic Neurons

Abstract: Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to … Show more

Help me understand this report
View preprint versions

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1

Citation Types

0
11
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
6
1

Relationship

2
5

Authors

Journals

citations
Cited by 27 publications
(11 citation statements)
references
References 83 publications
(115 reference statements)
0
11
0
Order By: Relevance
“…Complex functions, such as full adder and multiplication/factorization, were also suggested, showing the methodology’s potential to be applied to more complex logic circuits. Finally, a comparison between other p-computing hardware and this work is shown in Table 2 18 , 46 , 52 , 53 . The average power consumption of the p-bit circuit was calculated using the pulse output of the device (Supplementary Fig.…”
Section: Discussionmentioning
confidence: 99%
“…Complex functions, such as full adder and multiplication/factorization, were also suggested, showing the methodology’s potential to be applied to more complex logic circuits. Finally, a comparison between other p-computing hardware and this work is shown in Table 2 18 , 46 , 52 , 53 . The average power consumption of the p-bit circuit was calculated using the pulse output of the device (Supplementary Fig.…”
Section: Discussionmentioning
confidence: 99%
“…It has been shown both theoretically 24,25 and experimentally 26,27 that s-MTJ-based p-bits can be designed to generate new random numbers in times ∼ nanoseconds. The same circuit could also be used with other fluctuating resistors 28 , but one advantage of s-MTJ's is that they can be built by modifying magnetoresistive random access memory (MRAM) technology that has already reached gigabit levels of integration 29 .…”
Section: Methodsmentioning
confidence: 99%
“…On the other hand, using nanodevices such as CMOScompatible stochastic magnetic tunnel junctions (sMTJ), millions of p-bits can be accommodated in single cores due to the scalability achieved by the MRAM technology, exceeding 1Gbit MRAM chips [56,57]. However, before the stable MTJs can be controllably made stochastic, challenges at the material and device level must be addressed [58,59] with careful magnet design [60][61][62]. Different flavors of magnetic p-bits exist [63][64][65][66], for a recent review, see Ref.…”
Section: Hardware: Physical Implementation Of P-bits a P-bitmentioning
confidence: 99%