Voltage handling capability and termination techniques of silicon power semiconductor devices

Abstract

In a first part, we revisit the methodology used to calculate the avalanche breakdown voltage of power semiconductor devices. We show that the classical formulations using Van Oversraeten ionisation coefficient can lead to an underestimation of about 45% regarding the voltage handling capability.We next present a review of the major termination techniques used today in microelectronics, mainly planar compatible. Their principle will be shown and some general considerations about their drawbacks and advantages given. A comparison will be given regarding some criteria such as their static and dynamic efficiency, the space used, the voltage range covered, the ease of design and the technological feasibility.

Design of Trench MIS Field Plate Structure for Edge Termination of GaN Vertical PN Diode

“…Due to the high critical electric field of GaN, the dielectric breakdown of the MIS region must be carefully considered when determining the thickness of the MIS layer. The electric field strength inside the MIS region is determined via the relative permittivity of the insulator material and its thickness, which can be calculated using Gauss' law [8,9,37,38]. The third boundary condition is as follows: "The electric field inside the MIS layer must be lower than the critical electric field of the insulator with a sufficient safety margin".…”

“…Various edge termination techniques have been developed for Si and SiC power devices, such as junction termination extension, guard ring, field plate (FP), trench termination, floating field rings, etc. [8][9][10][11][12][13][14][15][16][17]. While ion implantation-based edge termination processes are widely used for Si and SiC power devices, they are extremely difficult to apply to a GaN device process.…”

Physical Limitations of Semiconductor Devices

“…Several other architectures are based on implementation of different junction termination [12], reduced surface field (RESURF) techniques and multi-RESURF or so-called super-junction techniques [13,14]. Several other architectures are based on implementation of different junction termination [12], reduced surface field (RESURF) techniques and multi-RESURF or so-called super-junction techniques [13,14].…”

Comparison of ESD protection capability of lateral BJT, SCR and bidirectional. SCR for hi-voltage BiCMOS circuits

“…The core bidirectional SCR (or DIAC -diode ac switch [l]) has been formed on N-epi substrate by symmetrical double PBODY implant regions. A number of junction termination techniques [3] have been evaluated (Fig. 1).…”