Wafer charging monitored by high frequency and quasi-static C−V measurements

En, Bill; Cheung, N.W.

doi:10.1016/0168-583x(93)95067-f

Cited by 10 publications

(2 citation statements)

References 5 publications

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“…For the 1 kHz case only a small voltage variation occurs because the plasma has almost enough time to equilibrate between pulses. In support of this simulation result, previous experimental work has shown that low repetition rates does not affect the charging damage to thin oxides [14]. Fig.…”

Section: Oxide Voltage Variation Due To Piiisupporting

confidence: 85%

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Modeling and experiments of waveform effects on oxide charging in plasma immersion ion implantation [MOS ICs]

Cheung

1997

IEEE Trans. Electron Devices

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An analytical model of the time-dependent currents of a plasma allows the determination of the physical mechanisms and dependencies of charging damage in Plasma Immersion Ion Implantation (PIII). From the model, we determine that the plasma requires several ms to equilibrate after the application of an implantation voltage pulse. Although the individual pulses only change the surface potential by a fraction of a volt, the long equilibration time means that the pulse repetition rate perturbs the time-averaged surface potential. A physical relation describing the dependence of the time-averaged surface potential on plasma and voltage bias parameters predicts that a shorter pulse width, lower electron temperature, and rectangular pulse shape maximizes the allowable implantation rate and minimizes the charging damage. For a given pulse shape and plasma condition, a maximum pulse repetition rate exists. Beyond this threshold frequency. the oxide fails because the oxide field exceeds its breakdown value. Experimental results corroborate the simulation's predictions, showing the dependence of the pulsing repetition rate on charging damage.

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Section: Oxide Voltage Variation Due To Piiisupporting

confidence: 85%

“…In all of these PIII processes devices on the Si wafers are exposed to both a plasma and ion implantation, resulting in potential oxide charging effects. Though plasma electrons are able to neutralize accumulated positive surface charge, charging damage can still be induced in certain cases [14].…”

Section: Introductionmentioning

confidence: 99%

Modeling and experiments of waveform effects on oxide charging in plasma immersion ion implantation [MOS ICs]

Cheung

1997

IEEE Trans. Electron Devices

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Silicon Device Processing

Kwong

2013

Materials Science and Technology

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The sections in this article are Introduction Gettering Intrinsic Gettering Gettering by Hydrogen Annealing Device Isolation LOCOS ‐Based Isolation Advanced Isolation Techniques Silicon‐on‐Insulator Gate Dielectrics Preoxidation Cleaning Process Dependence of Gate Oxide Quality Chemically Modified Gate Oxides CVD and Stacked Oxides Shallow Junction Formation Ion Implantation Advanced Techniques for p + ‐ n Junction Formation Diffusion from Doped Deposited Layers Gas Immersion Laser Doping Gas Phase Diffusion Plasma Immersion Ion Implantation Metallization Gate Electrodes Contacts Interconnections Planarization for Multilevel Interconnections Cluster Tool Technology Advantages Rapid Thermal Processing In Situ Dry Cleaning Interface Engineering Gate Stack of Oxide and Oxynitride Deposition of DRAM Storage Dielectrics Selective Deposition Processes Ultra‐Shallow Junction Formation Integrated CMOS Processing Based on RTP Ge x Si 1− x / Si Heteroepitaxy by RT ‐ CVD Single‐Wafer Integrated Processing

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Silicon Device Processing

Kwong

2000

Handbook of Semiconductor Technology Set

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Wafer charging monitored by high frequency and quasi-static C−V measurements

Cited by 10 publications

References 5 publications

Modeling and experiments of waveform effects on oxide charging in plasma immersion ion implantation [MOS ICs]

Modeling and experiments of waveform effects on oxide charging in plasma immersion ion implantation [MOS ICs]

Silicon Device Processing

Silicon Device Processing

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