Wafer level compression molding compounds

Abstract

Recently, electronic products are becoming smaller and thinner. In parallel, semiconductor packages inside the electronic products are also more miniaturized and thinner. In 2006, Infineon has invented new package configuration, which is fan out type wafer level packages called embedded wafar-level ball grid array (eWLB). At this moment, liquid molding compounds are mainly used for eWLB as encapsulant. However, liquid molding compounds have some problems like expensive material cost, high warpage, high die stand-off caused by molding shrinkage, and so on.In this work, advantages of solid molding compounds were confirmed for fan out wafer level package. Comparing to liquid compound, our developed solid compound had better results in warpage of molded wafer. Warpage behavior of molded wafer over the assembly process such as redistribution process or ball attach process was stable. Package warpage of developed solid compound was almost flat over the temperature. It was confirmed that high filler content was necessary for large area compression molding to prevent warpage issue. Liquid molding compound often shows high die stand-off, formation of reaction layer between liquid compound and thermal release tape which could affect following redistribution process. In the case of developed solid compound, neither die stand-off nor reaction layers were detected after debonding the thermal release tape. Compatibility between the developed solid molding compound and dielectric material for redistribution process was confirmed to be good with Polyimide, PBO, another low temperature curable dielectric material, and build-up material which were produced by HD MicroSystems and Hitachi Chemical. The molded package made with various dielectric materials successfully passed 1000 cycles of temperature cycle test (-55-125degC air to air), 336 hour of unbiased highly accelerated stress test (uHAST), and moisture sensitivity level 1 (MSL1) test.In this work, moldability of wafer level compression mold underfill material with flip chip stacked die was also confirmed. This material could be used for 2.5D/3D through silicon via (TSV) structures. Wafer level compression over mold and mold underfill were done at one molding step. Optimization of filler distribution and size of filler top cut were confirmed to be important for good underfilling.

Investigation of warpage in wafer-level Molding: Measurements and FE analysis

“…A number of technologies (ex: Fan-Out Wafer Level Packaging (FO-WLP) by Hitachi Chemical [1] and the stacked Through-Silicon Via with Wafer-Level Chip Scale Package (TSV-WCSP) by Texas Instruments [2]) have been developed on the basis of two major packaging trends identified as having low-cost potential: 3D integration of vertically stacked dies and large area embedding of laterally spaced dies. Compression molding is one packaging technique currently being considered in order to achieve large area die embedding.…”