Wafer lot release policies based on the continuous and periodic review of WIP levels

El-Kilany, Khaled S.

doi:10.1109/ieem.2011.6118206

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…For ease of simulation and comparison, the Intel Five Machine Six Steps (Mini Fab) is commonly used, e.g. [17], [22], [24]. It includes re-entrant flows, batch processors, machine failures, set-ups, and two main products, as well as one test wafer product.…”

Section: Literature Review -State-of-the-art In Researchmentioning

confidence: 99%

Order Release Methods in Semiconductor Manufacturing: State-of-the-Art in Science and Lessons from Industry

Lohmer¹,

Flechsig²,

Lasch³

et al. 2020

2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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The project iDev40 has received funding from the ECSEL Joint Undertaking under grant agreement No 783163. The JU receives support from the European Union's Horizon 2020 research and innovation programme. It is co-funded by the consortium members, grants from Austria, Germa-ny, Belgium, Italy, Spain and Romania. It is coordinated by Infineon Technologies Austria AG. The content of this article does not reflect the official opinion of the Joint Undertaking ECSEL. Responsibility for the information and views expressed in the article lies entirely with the authors.

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Section: Literature Review -State-of-the-art In Researchmentioning

confidence: 99%

Order Release Methods in Semiconductor Manufacturing: State-of-the-Art in Science and Lessons from Industry

Lohmer¹,

Flechsig²,

Lasch³

et al. 2020

2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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A new release control policy (WRELM) for semiconductor wafer fabrication facilities

Chen

Pan

et al. 2014

Proceedings of the 11th IEEE International Conference on Networking, Sensing and Control

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Release control plays an important role on the performance of a semiconductor wafer fabrication facility. Comparing to common release control strategies (such as FIFO, EDD, SA, CONWIP, WR, and WIPCTRL), a new workload regulating policy (abbreviated as WRELM), with a dynamic critical value on the bottleneck obtained by an extreme learning machine, is proposed. WRELM is validated and verified by a simulation model from a real 6 inch fab. The simulation resultsshow that WRELM improves the throughput by 4.02% and decrease the mean cycle time by 15.40% comparing to those of common WR.

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Simulation-Based Evaluation of Lot Release Policies in a Power Semiconductor Facility – a Case Study

Henriette

Flechsig

Lohmer

et al. 2020

2020 Winter Simulation Conference (WSC)

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Lot release policies, i.e., the decision which lots to start in production, in what quantity and at what time, have a significant influence on fab performance. Recent research focused on closed-loop policies. However, most studies only demonstrated the feasibility in settings with low-mix or low-volume simulation testbeds. In this paper, we focus on a real-world pre-assembly facility in a high-volume and high-mix semiconductor wafer fab. We conduct an in-depth, deterministic discrete-event simulation in two stages, using real production data and demands. First, we test two existing open-loop lot release policies (random and constant release) against a simple closed-loop release policy. Significant improvements in on-time delivery, bottleneck utilization, and throughput are notable. Second, we compare three closed-loop release policies and indicate which policy provides the best results for certain KPIs like enhanced on-time delivery or reduced tardiness.

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Wafer lot release policies based on the continuous and periodic review of WIP levels

Cited by 3 publications

References 16 publications

Order Release Methods in Semiconductor Manufacturing: State-of-the-Art in Science and Lessons from Industry

Order Release Methods in Semiconductor Manufacturing: State-of-the-Art in Science and Lessons from Industry

A new release control policy (WRELM) for semiconductor wafer fabrication facilities

Simulation-Based Evaluation of Lot Release Policies in a Power Semiconductor Facility – a Case Study

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