Wafer-scale integration using restructurable VLSI

Anderson, Allan; Raffel, J.I.; Wyatt, P.W.

doi:10.1109/2.129046

Cited by 11 publications

(11 citation statements)

References 12 publications

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“…The important advantage of laser linking over transistor switches is that the result is permanent and of lower impedance than the bidirectional transistor switches[l3]. Laser link defect avoidance has built fully operational Wafer scale circuits in 6 different designs applied to DSP filter and speech recognition systems [3,4], These were packaged using large multichip module type metal packages.…”

Section: Laser Link Defect Avoidancementioning

confidence: 99%

“…In commercial devices, such as DRAM's with areas of about 15x15 mm, this has lead to significantly enhanced yields. In more experimental applications laser defect avoidance has expanded usable silicon real estate into Wafer Scale Integration (WSI) device areas 25 square centimeters [3] [4].…”

Section: Introductionmentioning

confidence: 99%

“…In both cases the general design philosophy iS to break the overall structure into redundant cells (blocks) surrounded by communication buses and switches to route signals between the various cells [3]. These cells may range from repetitive blocks of memory to complex processing elements (for example in systolic Permission to make digital/hard copies of all or part ofthis mat&al for Pe=onal Or classroom use is granted without fee provided that he copies arc not made or dishibuted for profit or commercial advantage, he copyright notice.…”

Section: Introductionmentioning

confidence: 99%

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Laser correcting defects to create transparent routing for large area FPGA's

Chapman

Dufort

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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Creating large area FPGA's is limited by the presence of defective sections. The techniques developed in wafer scale work solve this problem by using defect avoidance routing around flawed blocks to build complete working systems. FPGA's have the main features required for successful defect avoidance systems: a repeatable cell, built in need for switchable flexible routing and high fiexibility with potentially large number of applications. Laser formed connections and cuts have proved to be effective in bypassing fabrication time defects and creating defect free working systems up to wafer scale in area. Power shorts and clock distribution errors can effectively be eliminated using these laser links. In addition it is important to minimize signal delays so the bypassing of the defective cells is nearly invisible. Experiments on a small test FPGA shows defect avoidance routing using laser link structures generates delays which are about half those obtained by the active switches required for the FPGA's operation. Thus laser defect avoidance after fabrication removes the errors creating a large area FPGA whose defective cell distribution is nearly unseen by the user.

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Section: Laser Link Defect Avoidancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Laser correcting defects to create transparent routing for large area FPGA's

Chapman

Dufort

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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“…Indeed, the main goal of the WaferIC is to provide a smart active interconnect area that can be configured in a short period of time, and that is large enough to implement a densely interconnected system, possibly composed of multiple ICs having more than 2,000 pins each. Wafer-scale integration feasibility has been demonstrated and several design rules that contribute to make it feasible have been defined as well (Landis, 1990;Boulori, 1991;Anderson, 1992;Koren, 1998;Sharifi, 2007). Moreover fault-tolerance and yield enhancement of WSI have been addressed in (Lea, 1988;Chen, 1994;Moore, 1985) as well as fundamental design methodologies for wafer scale integration in (Hedge, 1991).…”

Section: Introductionmentioning

confidence: 99%

Wafer-Scale Rapid Electronic Systems Prototyping Platform

Guillemot¹,

Nguyen²,

Bougataya³

et al. 2017

Novel Advances in Microsystems Technologies and Their Applications

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“…Wafer-scale integration feasibility has been demonstrated and several design rules that contribute to make it feasible have been defined as well (Landis, 1990;Boulori, 1991;Anderson, 1992;Koren, 1998;Sharifi, 2007). Moreover fault-tolerance and yield enhancement of WSI have been addressed in (Lea, 1988;Chen, 1994;Moore, 1985) as well as fundamental design methodologies for wafer scale integration in (Hedge, 1991).…”

Section: Introductionmentioning

confidence: 99%