2006
DOI: 10.1149/1.2135209
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Wafer Scale Packaging of MEMS by Using Plasma-Activated Wafer Bonding

Abstract: Plasma-assisted direct bonding has been investigated for wafer scale encapsulation of microelectromechanical systems ͑MEMS͒. Direct bonding requires smooth and flat wafer surfaces, which is seldom the case after fabrication of MEMS devices. Therefore, we have used polished chemical vapor deposited oxide as an intermediate bonding layer. The oxide layer is polished prior to bonding the MEMS wafer to cap silicon wafer. The bonding is carried out with plasma-assisted direct wafer bonding at a low temperature ͑Ͻ30… Show more

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Cited by 23 publications
(17 citation statements)
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“…The degassing issue seems to be significant for silicon oxide deposited by techniques such as PECVD and LPCVD but not for thermally grown oxide [15]. It has been demonstrated that patterned films can produce void-free bonds, even without densification, because grooves provide escape paths for gases produced during the bond-annealing step [16]- [19].…”
Section: Film Densificationmentioning
confidence: 99%
“…The degassing issue seems to be significant for silicon oxide deposited by techniques such as PECVD and LPCVD but not for thermally grown oxide [15]. It has been demonstrated that patterned films can produce void-free bonds, even without densification, because grooves provide escape paths for gases produced during the bond-annealing step [16]- [19].…”
Section: Film Densificationmentioning
confidence: 99%
“…It refers to the technology of packaging a sensor or an integrated circuit at wafer level [2], instead of chip scale packaging, the process of assembling the package of each individual unit after wafer dicing. WLP can offer reduction in cost, give high throughput and increased reliability by high-quality front-end sealing.…”
Section: Introductionmentioning
confidence: 99%
“…(a) First, the wafer was thermally oxidized to a thickness of 500 nm or 1 lm as electrical insulation and diffusion barrier between Pt and Si; (b) Pt thin film was sputtered directly on the substrate up to a thickness of 1 lm without adhesion layers (Käpplinger et al 2007); (c) the wafer was coated by photoresist and structured by photolithography; (d) about 900 nm of Pt was etched through ion beam etching (with a tilt of 20°to enhance the etching rate); (e) the residual Pt was etched in aqua regia (to avoid trench formation and possible short cut between Pt and Si); (f) optionally the wafer was coated with CVD-SiO 2 and CMP planarized to allow the direct wafer bonding (Jia et al 2006;Suni et al 2006); (g) the wafer was diced into single chips; (h) five holes were bored into the chip. Optionally the chip was thermally insulated through laser ablation; (i) when coated with CVD-SiO 2 , the coating layer covering the contact pads was removed with local HF-etching.…”
Section: Fabricationmentioning
confidence: 99%
“…3.3). In the future, the established fabrication process will be extended with direct wafer bonding as assembling method (Jia et al 2006;Suni et al 2006). …”
Section: Fabricationmentioning
confidence: 99%