Low-temperature bonding of Si wafers has been studied utilizing reactive ion etching-mode plasma activation. The hydrophilic Si and thermally oxidized Si wafers were exposed to N 2 , Ar, or O 2 plasma prior to bonding in air or vacuum. After plasma treatment the wafers were cleaned in RCA-1 solution and/or deionized water. Strong bonding was achieved at 200°C with all the investigated plasma gases, if proper bonding and cleaning procedures were used. Extended RCA-1 cleaning deteriorated the bond strength, but a short cleaning improved bonding. We found that the activation of the thermal oxide has a larger influence on the bond strength than the activation of the native oxide surface in Si/oxide wafer pairs. We suggest that the plasma treatment induces a highly disordered surface structure, which enhances the diffusion of the water from the bonded interface. As a result of the plasma exposure the number of the surface OH groups is greatly increased enabling strong bonding at a low temperature.

We report on detailed room-temperature transport properties of a 17nm thick double-gate silicon-on-insulator (DGSOI) transistor. We find that when the electron gas is transferred between the top and the bottom of the silicon-on-insulator (SOI) layer by changing the gate bias symmetry (i.e., applying the gate biases in a push–pull fashion), while keeping the carrier density constant the maximum mobility occurs when the electron gas symmetrically occupies the whole SOI slab. The observed mobility behavior is the fingerprint of volume inversion∕accumulation. This gate bias symmetry dependency of the mobility suggests that DGSOI devices intrinsically can be operated in a velocity modulation transistor (VMT) mode. In the experimental gate bias window, the maximum velocity∕mobility modulation is ∼40%. The VMT transconductance exceeds conventional single-gate transconductance when electron density is above ∼5.3×1016m−2. Improvements of the observed VMT operation in thin DGSOI devices are discussed.

Mechanically induced layer transfer of single-crystal silicon by hydrogen ion implantation, low-temperature wafer bonding, and subsequent mechanical splitting of the implanted wafer has been investigated. The bond strength measurements using the crack opening method in room environment yield a surface energy of ⩾2000 mJ/m2 after exposure to oxygen plasma and subsequent hydrophilic silicon/silicon dioxide bonding at 200 °C. Mechanically induced layer transfer was carried out for silicon wafers implanted to a dose of 5×1016 H2/cm2 at 100 keV and annealed for 2 h at 200 °C. No feature was observed by atomic force microscopy (AFM) measurements on the unbonded free surface after this heat treatment. For lower doses of implantation, annealing at higher temperatures is required to enable the mechanical transfer. AFM measurements on the split silicon surface indicate that low-temperature wafer bonding and mechanical transfer yield a root mean square surface roughness of 4 nm which is less than in the standard Smart-Cut® process.

Plasma-assisted direct bonding has been investigated for wafer scale encapsulation of microelectromechanical systems ͑MEMS͒. Direct bonding requires smooth and flat wafer surfaces, which is seldom the case after fabrication of MEMS devices. Therefore, we have used polished chemical vapor deposited oxide as an intermediate bonding layer. The oxide layer is polished prior to bonding the MEMS wafer to cap silicon wafer. The bonding is carried out with plasma-assisted direct wafer bonding at a low temperature ͑Ͻ300°C͒. Two different methods to form electrical contacts to the encapsulated device are presented. In the first method trenches are etched on the surface of the cap wafer before the bonding. During the bonding the trenches are aligned to the contact pads of the device wafer. After bonding the cap wafer is thinned down with grinding until the path to the contact pads is opened. In the second method one or both of the wafers are thinned down to around 100 m after bonding. The electrical path to contact pads is formed using V-groove sawing, metal sputtering, and lithography. To test the viability of the developed methods for MEMS encapsulation, we have sealed polysilicon resonator structures at a wafer level.

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