WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks

Han, Kyuhwa; Kim, Hyukjoong; Shin, Dongkun

doi:10.1109/tc.2019.2947897

Cited by 21 publications

(2 citation statements)

References 22 publications

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“…A survey paper [42] provides a broad overview of some typical address translation technologies for flash memories [19,25,50,54]. Among them, page-level mapping shows the best performance due to fine-grained mapping, but it requires a large mapping table [9,10,21,44,47,48,62,63]. The existing mapping schemes share a common design principle: exploiting the workload locality to selectively cache a small part of mapping entries in DRAM while storing the whole mapping table on flash.…”

Section: Mapping Schemes In Ftl Designmentioning

confidence: 99%

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

Wang¹,

Lin²,

Wu³

et al. 2023

Preprint

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We present LearnedFTL, which applies learned indexes to on-demand page-level flash translation layer (FTL) designs to improve the random read performance of flash-based solidstate drives (SSDs). The first of its kind, it minimizes the number of double reads induced by address translation in random read accesses. To apply the learned indexes to address translation, LearnedFTL proposes dynamic piece-wise regression to efficiently build learned indexes. LearnedFTL also exploits the unique feature of page relocation in SSD internal garbage collection (GC), and embeds the learned index training in GC, which can minimize additional delay on normal read and write operations. Additionally, LearnedFTL employs a bitmap prediction filter to guarantee the accuracy of learned indexes' predictions. With these designs, LearnedFTL considerably speeds up address translation while reducing the number of flash read accesses caused by the demand-based page-level FTL. Our benchmark-driven experiments on a FEMU-based prototype show that LearnedFTL reduces the 99th percentile tail latency by 4.8×, on average, compared to the state-of-the-art TPFTL scheme.

show abstract

Section: Mapping Schemes In Ftl Designmentioning

confidence: 99%

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

Wang¹,

Lin²,

Wu³

et al. 2023

Preprint

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show abstract

“…An SSD consists of a controller ASIC (Application Specific Integrated Circuit) and a group of flash memory chips. Usually, a data stream is stripped among these flash memory chips using multiple flash channels [7,8,9,10,11,12,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

Embedded multiport data buffer for a solid-state drive controller

Liu

Fan

Luo

et al. 2021

IEICE Electron. Express

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Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today's standards; however, they are small, low cost and consume little power. SSD controllers are thus designed as DRAM-less chips. SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port. In an SSD controller, more than two IPs simultaneously access the same SRAM, such as the CPU, data interface, and multiflash memory channel. It is thus complicated to exchange data between multiple ports. A new architecture of the multi-port data buffer (M-Buffer) is proposed in this study to solve this problem. M-Buffer is composed of wide SRAM, a smart arbitrator and several interface port logics. The M-Buffer can be designed as a reusable architecture and is small, low cost and consumes little power.

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Efficient persistent memory file systems using virtual superpages with multi-level allocator

Yang

Zhang

et al. 2022

Journal of Systems Architecture

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WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks

Cited by 21 publications

References 22 publications

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

LearnedFTL: A Learning-based Page-level FTL for Improving Random Reads in Flash-based SSDs

Embedded multiport data buffer for a solid-state drive controller

Efficient persistent memory file systems using virtual superpages with multi-level allocator

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