Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

Lau, John H.; Li, Ming; Tian, Dewen; Fan, Na; Kuah, Eric; Wu, Kai; Li, Margie; Hao, Ji; Cheung, Yiu-ming; Li, Zhang; Tan, K. H.; Beica, Rozalia; Taylor, T.A.; Ko, Cheng-Ta; Yang, Henry; Chen, Yuhua; Lim, Sze Pei; Lee, Ning Cheng; Jiang, Runqing; Cao, Xi; Wee, Koh Sau; Yong, Qingxiang

doi:10.1109/tcpmt.2017.2715185

Cited by 94 publications

(9 citation statements)

References 18 publications

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“…Figure 21 schematically shows the top view and crosssectional view of the FOWLP structure shown in Fig. 18 for thermal analyses [79,80]. It can be seen that the chip size is The ambient temperature is assumed to be 25 C. The boundary condition on the top side and bottom side of the PCB and the top side of the chip is with a convective heat transfer coefficient, h ¼ 10 W/m 2 K, which is to imitate a natural convection condition.…”

Section: Thermal Performance Of Chip-first (Die Face-up)mentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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Section: Thermal Performance Of Chip-first (Die Face-up)mentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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“…FOWLP has attracted the interest of many scholars: extensive researches on warpage prediction [17][18][19][20], thermal performance [21,22] and electrical performance [23][24][25][26] have been carried out. Electrical performance is significant for millimeter-wave applications, such as the 77 GHz automotive radar and wireless communication systems.…”

Section: Introductionmentioning

confidence: 99%

Design for the Package-Board Transition and Its Testability Design in the Fan-Out Wafer-Level Package

Chen

Cao

2022

Electronics

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A fan-out wafer level package (FOWLP) with double-sided four redistribution layers (RDLs) and the mega pillars connecting the front and back RDLs has been proposed for millimeter-wave applications. A well-matched package-board transition has been designed in this paper. The simulated insertion loss for the transition is about 0.82 dB at 79 GHz, and the simulated return loss is better than 10 dB from 72 GHz to 86 GHz. More importantly, two different measurement methods based on the port reduction technique and the Thru-Reflect-Line (TRL) calibration technique have been proposed to get the S parameters of the transition. Moreover, the feasibility of the two methods has been verified by simulation.

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“…The fan-out package structure has good electrical and thermal performance and is used in many applications for system integration. Moreover, packaging-on-packaging (PoP) technology allows packages to be stacked three-dimensionally, thus achieving high-density integration and improving chip-to-chip performance (e.g., in applications with high-frequency data exchange between application processes and memory) [ 1 , 2 , 3 ].…”

Section: Introductionmentioning

confidence: 99%

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

2021

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The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

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Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

Cited by 94 publications

References 18 publications

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Design for the Package-Board Transition and Its Testability Design in the Fan-Out Wafer-Level Package

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

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