Warpage Suppression during FO-WLP Fabrication Process

Takekoshi, Masaaki; Nishido, Keisuke; Okada, Yoji; Suzuki, N.; Nonaka, Takamasa

doi:10.1109/ectc.2017.133

Cited by 19 publications

(2 citation statements)

References 7 publications

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“…Grinding was conducted to eliminate overburden over-mold and achieve the desired thickness. Takekoshi et al (2017) investigated FOWLPs. The EMC thickness was 500 mm and was ground to 200 mm so that the dies backsides were exposed.…”

Section: Research Studiesmentioning

confidence: 99%

Recent advances and applications of abrasive processes for microelectronics fabrications

Zhong

2019

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Purpose This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications. Design/methodology/approach More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs). Findings Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding. Originality/value This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

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Section: Research Studiesmentioning

confidence: 99%

Recent advances and applications of abrasive processes for microelectronics fabrications

Zhong

2019

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“…The viscoelastic property of the molding material was considered. Takekoshi et al [ 16 ] studied the effects of composing a material combination of an RDL-first-type FOWLP with various die occupancy ratios during the fabrication processes on warpage through both experiments and numerical simulation. The results showed that the warpage could be controlled within 1 mm during all the fabrication process steps.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process

Chen

et al. 2022

Materials

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This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

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