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To achieve the recent improvements in miniaturization and performance of mobile devices (Smart phone, Tablet PC etc.), the semiconductor PKG substrate installed in these devices is demanded to be thinner and higher in density. However, the thinner PKG substrate may cause poor connection reliability due to increased warpage by soldering. The ultra low CTE (Coefficient of thermal expansion) core material has been required as the key solution for the reduction of the warpage of the thinner PKG substrate such as PoP (Package on package).We have just developed two types of ultra low CTE core materials named E-705G and E-800G to meet with the requirement, applying our original resin systems and the filler surface treatment technologies.The developed materials show the ultra low CTE(X,Y) property (2.8-3.3 ppm/ o C) similar to that of glass fabric itself. Also E-705G has high flexural modulus over 33-36 GPa at room temperature. Regarding E-800G, it has the good dielectric characteristics (lower dielectric constant and dissipation factor), can be applicable higher speed PKG. Both of the materials have high reliability and high heat resistance which is suitable for the lead-free soldering process.Confirming the warpage property, we evaluated the warpage behavior of PoP (bottom) constructions before/after assembly process. The newly developed materials showed the much lower warpage than the conventional low CTE material.

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We developed a simple method for accurately predicting the warpage of the ball grid array (BGA) interposer in consideration of the wiring layers. In recent years, this interposer has become thinner, so the influence of the wiring layers has become larger. Consequently, modeling the wiring layers is important for predicting the warpage of the BGA package. However, detailed modeling of the wiring layers causes an increase of the analysis scale. For this reason, we calculated the anisotropic material properties of the wiring layers using the homogenization method. From this, we reveal that it is possible to achieve the same precision as that of a real wiring shape model while decreasing the analysis scale by using this method. We also reveal that this method is effective for high temperatures.

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