Watermarking ICs for IP protection

Newbould, Rexford D.; Irby, D.L.; Carothers, J.D.; Rodríguez, Jeffrey J.; Holman, W.T.

doi:10.1049/el:20020143

Cited by 26 publications

(8 citation statements)

References 2 publications

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“…Signature embedding by means of time constrains 8 consists of specifying timing constraints in paths different from the "critical path". All of these techniques, as well as those proposed in 4,9,10 , embed watermarks at the physical level.…”

Section: Protection Using Watermarking Strategiesmentioning

confidence: 99%

Watermarking strategies for IP protection of micro-processor cores

et al. 2010

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Reuse-based design has emerged as one of the most important methodologies for integrated circuit design, with reusable Intellectual Property (IP) cores enabling the optimization of company resources due to reduced development time and costs. This is of special interest in the Field-Programmable Logic (FPL) domain, which mainly relies on automatic synthesis tools. However, this design methodology has brought to light the intellectual property protection (IPP) of those modules, with most forms of protection in the EDA industry being difficult to translate to this domain. However, IP core watermarking has emerged as a tool for IP core protection. Although watermarks may be inserted at different levels of the design flow, watermarking Hardware Description Language (HDL) descriptions has been proved to be a robust and secure option. In this paper, a new framework for the protection of μP cores is presented. The protection scheme is derived from the IPP@HDL procedure and it has been adapted to the singularities of μP cores, overcoming the problems for the digital signature extraction in such systems. Additionally, the feature of hardware activation has been introduced, allowing the distribution of μP cores in a "demo" mode and a later activation that can be easily performed by the customer executing a simple program. Application examples show that the additional hardware introduced for protection and/or activation has no effect over the performance, and showing an assumable area increase.

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Section: Protection Using Watermarking Strategiesmentioning

confidence: 99%

Watermarking strategies for IP protection of micro-processor cores

et al. 2010

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“…This last watermarking technique is used in combination with "tiling" algorithms [12][13] , to divide the design into a set of tiles with different logic block configurations. All of these techniques, as well as those proposed in [14][15] , embed watermarks at the physical level. Physical level watermarks should not be an exclusive domain for IPP, since in that case only the solution to the physical design is protected.…”

Section: Classification Of the Watermarking Techniques: State Of The Artmentioning

confidence: 99%

“…This watermarking technique consists on spreading all the possible bits of a digital signature through both, used or non used cells of memory structures included in the HDL description of the design. As the signature spreading is performed at the high-level design description stage, this method is more secure than other IPP techniques [14][15] because the signature propagates through the whole design flow down to the physical implementation. In addition, the fact that in the proposed watermarking technique the signature is spread in memory structures that are part of the design, with the signature bits being interlaced with the data required by the circuit to operate, makes extremely difficult the possibility of an attacker finding and removing these signature bits.…”

Section: Hdl-level Watermarking Strategiesmentioning

confidence: 99%

Intellectual property protection of IP cores through high-level watermarking

et al. 2007

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In this paper a watermarking technique for Intellectual Property Protection (IPP) of FPGA-based systems is proposed. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The proposed watermarking technique relies on a procedure that spreads the digital signature in cells of memory structures at Hardware Description Language (HDL) design level, not increasing the area of the system. This signature is preserved through synthesis, placement and routing processes. The technique includes a procedure for signature extraction requiring minimal modifications to the system. Thus, it is possible to detect the ownership rights without interfering the normal operation of the system and providing high invulnerability. To illustrate the properties of the proposed watermarking technique, both protected and unprotected design examples are compared in terms of area and performance. The analysis of the results shows that the area increase is very low while throughput penalization is almost negligible.

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“…Signature embedding by means of time constraints [8] consists of specifying timing constraints in paths different from the "critical path". All of these techniques, as well as those proposed in [3,[9][10], embed watermarks at the physical level. Physical level watermarks should not be an exclusive domain for IPP, since in that case only the solution to the physical design is protected.…”

Section: Ip Core Protectionmentioning

confidence: 99%

IPP Watermarking Technique for IP Core Protection on FPL Devices

Castillo

Parrilla

García

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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This paper presents a technique for Intellectual Property Protection (IPP) of systems to be implemented over programmable devices. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction requiring minimal modifications to the system. So it is possible to detect the ownership rights without interfering the normal operation of the system. The IPP technique has been implemented on FPL devices, not disrupting the functionality neither significantly degrading the performance.

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Watermarking ICs for IP protection

Cited by 26 publications

References 2 publications

Watermarking strategies for IP protection of micro-processor cores

Watermarking strategies for IP protection of micro-processor cores

Intellectual property protection of IP cores through high-level watermarking

IPP Watermarking Technique for IP Core Protection on FPL Devices

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